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1. 发明授权

US5384665A Data dividing apparatus 失效
标题翻译：数据分割装置
公开(公告)号：US5384665A
公开(公告)日：1995-01-24
申请号：US20325
申请日：1993-02-19
申请人： Ikuo Ohkuma , Makoto Kumano , Sadayuki Inoue , Ken Onishi , Junko Ishimoto
发明人： Ikuo Ohkuma , Makoto Kumano , Sadayuki Inoue , Ken Onishi , Junko Ishimoto
IPC分类号： G11B27/032 , G11B27/30 , H04N5/7826 , H04N7/26 , H04N7/30 , H04N9/797 , H04N9/804 , G11B5/02 , G11B5/00 , G11B5/09
CPC分类号： H04N9/8047 , G11B27/032 , G11B27/3063 , H04N19/124 , H04N19/152 , H04N19/187 , H04N19/37 , H04N19/60 , H04N19/13 , H04N19/146 , H04N19/30 , H04N19/91 , H04N5/78263 , H04N9/7973
摘要： Specified modular arithmetic is applied to input digital data to divide the input data into two main codes and a subcode. Otherwise, input digital data is divided into two pieces of digital data according to a specified rule. The digital data is divided so that the original input digital data can be completely restored if the two main codes and the subcode or both of the divided data are used, and the original input digital data can be nearly correctly restored even when one of the main codes or one of the divided data is used.
摘要翻译：应用指定的模数运算来输入数字数据，将输入数据分成两个主要代码和一个子代码。否则，输入数字数据按照规定被分成两部分数字数据。数字数据被分割，使得如果使用两个主要代码和子代码或两个分割数据，则原始输入数字数据可以被完全恢复，并且即使当主要代码或分割数据之一被使用。

2. 发明授权

US5675696A Digital video signal recording and reproducing apparatus 失效
标题翻译：数字视频信号记录和再现装置
公开(公告)号：US5675696A
公开(公告)日：1997-10-07
申请号：US546841
申请日：1995-10-23
申请人： Junko Ishimoto , Haruhisa Inoue , Makoto Kumano , Sadayuki Inoue
发明人： Junko Ishimoto , Haruhisa Inoue , Makoto Kumano , Sadayuki Inoue
IPC分类号： G11B15/18 , G11B27/032 , G11B27/036 , H04N5/783 , H04N9/804 , H04N9/888 , H04N5/926 , H04N5/92
CPC分类号： H04N9/8042 , G11B27/036 , G11B15/1875 , G11B2220/90 , G11B27/032 , H04N5/783 , H04N9/888
摘要： A digital video signal recording and reproducing apparatus which obtains a favorable reproduced picture even when the data overwritten by edited data is interpolated with the data of the preceding field or preceding frame by recording the video data of the visually inconspicuous peripheral area on a track that is possibly overwritten by the editing data at a cut-in point or cut-out point in assemble editing or insert editing. The apparatus further obtains a natural picture without any fixed error even in speed search mode by exchanging the recording order of the video data of one field on plural tracks according to the head scanning trace in the speed search.
摘要翻译：一种数字视频信号记录和再现装置，即使在通过编辑数据覆盖的数据被内插的情况下，通过将视觉上不显眼的周边区域的视频数据记录在在编辑或插入编辑时可能会在切入点或切出点处的编辑数据覆盖。通过在速度搜索中根据头部扫描轨迹交换多个轨道上的一个场的视频数据的记录顺序，装置还通过速度搜索模式获得无任何固定误差的自然图像。

3. 发明授权

US5504758A Error-correcting apparatus 失效
标题翻译：纠错装置
公开(公告)号：US5504758A
公开(公告)日：1996-04-02
申请号：US53497
申请日：1993-04-28
申请人： Sadayuki Inoue , Junko Ishimoto , Takahiko Nakamura , Makoto Kumano
发明人： Sadayuki Inoue , Junko Ishimoto , Takahiko Nakamura , Makoto Kumano
IPC分类号： H03M13/00 , H03M13/15 , G06F11/10
CPC分类号： H03M13/151 , H03M13/00
摘要： In an error-correcting apparatus for correcting errors included in reproduced data which are stored in a RAM, a syndrome generation circuit, a polynomial calculation circuit for calculating an error position polynomial and an error value polynomial, and a position calculation circuit for calculating an error position are operated in parallel. A divider section of the error-correcting apparatus has a divider for performing the division of highest-degree coefficients of two polynomials, a multiplier for multiplying the coefficient of the polynomial set in the divisor side of the divider by the output of the divider, and an adder for adding the output of the multiplier and the coefficient of the polynomial set in the dividend side of the divider. The divider section executes the division over a Galois field while sequentially shifting the contents of registers which store the coefficient data of the dividend polynomial.
摘要翻译：在用于校正存储在RAM中的再现数据中包含的误差的纠错装置，校正子产生电路，用于计算误差位置多项式的多项式计算电路和误差值多项式，以及用于计算误差的位置计算电路位置并行运行。误差校正装置的除法器部分具有用于执行两个多项式的最高系数的除法的分频器，用于将除法器的除数的多项式的系数乘以分频器的输出的乘法器，以及用于将乘法器的输出和分频器的被除数中的多项式的系数相加的加法器。分频器部分通过伽罗瓦域执行除法，同时顺序地移位存储分红多项式的系数数据的寄存器的内容。

4. 发明授权

US5778138A Magnetic recording and reproduction apparatus for preventing fixed pattern noise from appearing in a reproduced image when reproducing at high speed 失效
标题翻译：磁记录和再现装置，用于在高速再现时防止固定图案噪声出现在再现图像中
公开(公告)号：US5778138A
公开(公告)日：1998-07-07
申请号：US653921
申请日：1996-05-22
申请人： Junko Ishimoto , Sadayuki Inoue , Makoto Kumano
发明人： Junko Ishimoto , Sadayuki Inoue , Makoto Kumano
IPC分类号： G11B5/09 , G11B15/18 , G11B15/467 , G11B15/473 , H04N5/7826 , H04N5/783 , H04N9/797 , H04N9/804 , H04N5/91
CPC分类号： G11B15/1875 , G11B15/4671 , H04N5/783 , H04N9/7973 , H04N9/8047
摘要： A magnetic recording and reproduction apparatus wherein the drum motor is controlled so that the rotation number of the drum during playback at the normal speed multiplied by N (N is an integer) changes by a fixed factor to R(1+q/Q) (Q, q are integers satisfying .vertline.q.vertline.
摘要翻译：一种磁记录和再现装置，其中控制鼓电动机，使得以正常速度乘以N（N为整数）的重放期间的鼓的旋转数量以固定因子改变为R（1 + q / Q）（ Q，q是满足| q | <| Q |的整数，假定在正常播放期间滚筒的转数为R rpm。还有一种磁记录和再现装置，其中控制鼓马达，使得以正常速度乘以N（N为整数）的播放期间的滚筒的平均转数通过周期性地改变滚筒的转数而变为约R rpm 并且将正常重放期间的滚筒的旋转数作为R rpm，将R rpm以下的转数与R rpm以上的转速组合。

5. 发明授权

US5570378A Error-correcting apparatus 失效
公开(公告)号：US5570378A
公开(公告)日：1996-10-29
申请号：US505883
申请日：1995-07-24
申请人： Sadayuki Inoue , Junko Ishimoto , Takahiko Nakamura , Makoto Kumano
发明人： Sadayuki Inoue , Junko Ishimoto , Takahiko Nakamura , Makoto Kumano
IPC分类号： H03M13/00 , H03M13/15 , G06F11/10
CPC分类号： H03M13/151 , H03M13/00
摘要： In an error-correcting apparatus for correcting errors included in reproduced data which are stored in a RAM, a syndrome generation circuit, a polynomial calculation circuit for calculating an error position polynomial and an error value polynomial, and a position calculation circuit for calculating an error position are operated in parallel. A divider section of the error-correcting apparatus has a divider for performing the division of highest-degree coefficients of two polynomials, a multiplier for multiplying the coefficient of the polynomial set in the divisor side of the divider by the output of the divider, and an adder for adding the output of the multiplier and the coefficient of the polynomial set in the dividend side of the divider. The divider section executes the division over a Galois field while sequentially shifting the contents of registers which store the coefficient data of the dividend polynomial.

6. 发明授权

US5574570A Video signal recording/reproduction apparatus and method for recording/reproducing two kinds of video signals carrying different amounts of information 失效
标题翻译：用于记录/再现携带不同信息量的两种视频信号的视频信号记录/再现装置和方法
公开(公告)号：US5574570A
公开(公告)日：1996-11-12
申请号：US057774
申请日：1993-05-06
申请人： Ikuo Ohkuma , Makoto Kumano , Kihei Ido , Ken Onishi
发明人： Ikuo Ohkuma , Makoto Kumano , Kihei Ido , Ken Onishi
IPC分类号： G11B20/18 , G11B27/032 , G11B27/036 , G11B27/30 , H03M13/35 , H04N9/804 , H04N9/806 , H04N9/82 , H04N9/888 , H04N5/76 , G11B5/02 , H04N5/91
CPC分类号： G11B27/3027 , G11B20/1813 , G11B27/036 , H03M13/35 , H04N9/8042 , H04N9/8066 , H04N9/8227 , H04N9/888 , G11B2220/90 , G11B27/032
摘要： When recording HD video signals, twice the number of tracks are used as compared to recording the conventional NTSC video signals, and video signals are recorded in the audio sector. HD video signals are encoded with the same number of checks as the error-correcting code of the present video signals, with the number of information symbols being increased. When recording HD video signals and present video signals, these signals are encoded so that the shortest recording wavelength is the same with either signal.
摘要翻译：当记录高清视频信号时，与记录常规NTSC视频信号相比，使用两倍数量的磁道，并且视频信号被记录在音频扇区中。 HD视频信号用与当前视频信号的纠错码相同数量的检查进行编码，信息符号数量增加。当记录HD视频信号并呈现视频信号时，对这些信号进行编码，使得最短记录波长与任一信号相同。

7. 发明授权

US06173024B2 Bit stream reproducing apparatus 失效
标题翻译：比特流再现装置
公开(公告)号：US06173024B2
公开(公告)日：2001-01-09
申请号：US09070731
申请日：1998-05-01
申请人： Takahiro Nanba , Masashi Kuroda , Makoto Kumano
发明人： Takahiro Nanba , Masashi Kuroda , Makoto Kumano
IPC分类号： H04L2500
CPC分类号： H04L1/0061 , G10L19/005 , H04J3/0605
摘要： The bit stream reproducing apparatus is comprised of a frame length counter for measuring a data length of one frame; a first calculator for calculating a data length “L1” defined from a header to a scale factor; a second calculator for calculating a data length “L2” of an audio sample; and a third calculator for executing a calculation of E=F−(L1+L2×12) based upon calculation results of the first calculator and of the second calculator, and for sending out a control signal to a muting circuit so as to instruct a muting operation in the case of E
摘要翻译：比特流再现装置包括用于测量一帧的数据长度的帧长度计数器; 用于计算从标题到比例因子定义的数据长度“L1”的第一计算器; 用于计算音频样本的数据长度“L2”的第二计算器; 以及第三计算器，用于基于第一计算器和第二计算器的计算结果执行E = F-（L1 + L2×12）的计算，并且向控制信号发送控制信号以指示静音操作在E <0的情况下。

8. 发明授权

US06495977B2 Vertical deflection circuit, processor for vertical deflection, and CRT display 失效
公开(公告)号：US06495977B2
公开(公告)日：2002-12-17
申请号：US09919822
申请日：2001-08-02
申请人： Makoto Kumano
发明人： Makoto Kumano
IPC分类号： H01J2956
CPC分类号： H04N3/22 , H04N3/16
摘要： There is disclosed a vertical deflection circuit for use in a display device employing a CRT. The vertical deflection circuit has a DSP (digital signal processor) for producing a digital current signal during each main period. This digital current signal shows plural current values which increases in first equal increments from a different value during each main period. The digital current value is converted into an analog current signal by a D/A converter and then averaged by a low-pass filter. A vertical deflection current is produced based on the averaged analog current signal. Because plural different current values are averaged, the average value varies linearly. Accordingly, the vertical deflection current varies linearly with each main period.

9. 发明授权

US5065230A Video signal processor for simultaneously reproducing a plurality of video information on a single monitor picture tube 失效
标题翻译：视频信号处理器，用于在单个监视器显像管上同时再现多个视频信息
公开(公告)号：US5065230A
公开(公告)日：1991-11-12
申请号：US410320
申请日：1989-09-21
申请人： Makoto Kumano , Masaharu Hayakawa , Shinichi Suenaga
发明人： Makoto Kumano , Masaharu Hayakawa , Shinichi Suenaga
IPC分类号： H04N9/74 , H04N9/64 , H04N11/04
CPC分类号： H04N9/641 , H04N5/45
摘要： A video signal processing apparatus which includes a clock signal generator for generating a clock signal in synchronism with a color synchronizing signal contained in an incoming video signal. This clock signal has a frequency equal to a multiple of the frequency of the color synchronizing signal. An analog-to-digital converter operates in response to the clock signal to sample and convert an incoming composite video signal into a digital video signal. An address setting circuit is provided for generating an address signal synchronized with horizontal and vertical synchronizing signals. The apparatus also includes a memory having addresses controlled by the address signal, a write-in device for writing bits extracted out of a digital output signal from the analog-to-digital converter into the memory in synchronism with the clock signal, a read-out device having addresses adapted to be controlled by the address signal and for reading out a digital signal from the memory in synchronism with the color synchronizing signals, and a digital-to-analog converter for converting the read digital signal read into an analog signal. The bits have phases different from that of the color synchronizing signal, the differences in phase between the bits and the color synchronizing signal being continued at a predetermined bit interval.
摘要翻译：一种视频信号处理装置，包括时钟信号发生器，用于与包含在输入视频信号中的彩色同步信号同步地产生时钟信号。该时钟信号的频率等于彩色同步信号频率的倍数。模拟 - 数字转换器响应于时钟信号进行采样并将输入的复合视频信号转换为数字视频信号。提供地址设置电路，用于产生与水平和垂直同步信号同步的地址信号。该装置还包括具有由地址信号控制的地址的存储器，用于与来自模拟数字转换器的数字输出信号一起提取的位与时钟信号同步地写入到存储器中的写入装置，输出装置，其具有适于由地址信号控制的地址，并且用于与彩色同步信号同步地从存储器读出数字信号;以及数模转换器，用于将读取的读取的数字信号转换为模拟信号。这些位具有与彩色同步信号不同的相位，位之间的相位差和彩色同步信号以预定位间隔继续。

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