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    • 8. 发明授权
    • Methods of manufacturing a semiconductor device and a semiconductor memory device thereby
    • 因此制造半导体器件和半导体存储器件的方法
    • US08557661B2
    • 2013-10-15
    • US13314627
    • 2011-12-08
    • Han-Geun YuGyung-Jin MinSeong-Soo LeeSuk-Ho JooYoo-Chul KongDae-Hyun Jang
    • Han-Geun YuGyung-Jin MinSeong-Soo LeeSuk-Ho JooYoo-Chul KongDae-Hyun Jang
    • H01L29/78H01L21/336
    • H01L27/11565H01L21/0337H01L21/31144H01L21/32139H01L27/11575H01L27/11582
    • A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.
    • 一种制造半导体器件的方法包括在存储单元区域上形成存储单元,在连接区域上交替地形成牺牲层和绝缘中间层,以提供配置为电连接存储单元的布线,形成包括蚀刻掩模图案 在顶部牺牲层上的元件,在每个蚀刻掩模图案元件的每个侧壁上形成阻挡侧壁,形成第一光致抗蚀剂图案,选择性地将第一阻挡侧壁从存储器单元区域最远地覆盖并覆盖其它阻挡侧壁,蚀刻暴露顶部 牺牲层和绝缘中间层以暴露第二牺牲层,通过横向去除第一光致抗蚀剂图案至第二阻挡侧壁暴露的程度形成第二光致抗蚀剂图案,并将暴露的顶部和第二牺牲层和绝缘夹层蚀刻到 形成一个楼梯形状 d侧边缘部分。
    • 10. 发明授权
    • Tunable active inductor
    • 可调谐有源电感
    • US07253707B2
    • 2007-08-07
    • US11141123
    • 2005-05-31
    • Rajarshi MukhopadhySebastien NuttinckSang-Hyun WooJong-Han KimSeong-Soo LeeChang-Ho LeeJoy Laskar
    • Rajarshi MukhopadhySebastien NuttinckSang-Hyun WooJong-Han KimSeong-Soo LeeChang-Ho LeeJoy Laskar
    • H03H11/00H03H11/04
    • H03H11/50H03H11/48
    • An active inductor capable of tuning a self-resonant frequency, an inductance, a Q factor, and a peak Q frequency by applying a tunable feedback resistor to a cascode-grounded active inductor is disclosed. The tunable active inductor includes a first transistor having a source connected to a power supply voltage and a gate connected to first bias voltage; a second transistor having a drain connected to a drain of the first transistor and a gate connected to a second bias voltage; a third transistor having a drain connected to a source of the second transistor and a source connected to a ground voltage; a fourth transistor having a drain connected to a gate of the third transistor, a source connected to the ground voltage and a gate connected to a third bias voltage; a fifth transistor having a source connected to the drain of the fourth transistor and a drain connected to the power supply voltage.
    • 公开了一种通过将可调谐反馈电阻器施加到共源共栅接地有源电感器来调谐自谐振频率,电感,Q因子和峰值Q频率的有源电感器。 可调谐有源电感器包括具有连接到电源电压的源极和连接到第一偏置电压的栅极的第一晶体管; 第二晶体管,具有连接到所述第一晶体管的漏极的漏极和连接到第二偏置电压的栅极; 具有连接到所述第二晶体管的源极的漏极和连接到接地电压的源极的第三晶体管; 具有连接到第三晶体管的栅极的漏极的第四晶体管,连接到接地电压的源极和连接到第三偏置电压的栅极; 第五晶体管,其源极连接到第四晶体管的漏极,漏极连接到电源电压。