专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20190042159A1 OSCILLATOR CIRCUITRY TO FACILITATE IN-MEMORY COMPUTATION 审中-公开
公开(公告)号：US20190042159A1
公开(公告)日：2019-02-07
申请号：US16146878
申请日：2018-09-28
申请人： Ian YOUNG , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Abhishek SHARMA , Raghavan KUMAR , Phil KNAG , Huseyin SUMBUL , Gregory CHEN
发明人： Ian YOUNG , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Abhishek SHARMA , Raghavan KUMAR , Phil KNAG , Huseyin SUMBUL , Gregory CHEN
IPC分类号： G06F3/06 , H03K3/03 , G11C7/10
摘要： Techniques and mechanisms for a memory device to perform in-memory computing based on a logic state which is detected with a voltage-controlled oscillator (VCO). In an embodiment, a VCO circuit of the memory device receives from a memory array a first signal indicating a logic state that is based on one or more currently stored data bits. The VCO provides a conversion from the logic state being indicated by a voltage characteristic of the first signal to the logic state being indicated by a corresponding frequency characteristic of a cyclical signal. Based on the frequency characteristic, the logic state is identified and communicated for use in an in-memory computation at the memory device. In another embodiment, a result of the in-memory computation is written back to the memory array.

2. 发明申请

US20190205273A1 MEMORY DEVICE WITH MULTIPLE MEMORY ARRAYS TO FACILITATE IN-MEMORY COMPUTATION 审中-公开
公开(公告)号：US20190205273A1
公开(公告)日：2019-07-04
申请号：US16146534
申请日：2018-09-28
申请人： Jack KAVALIEROS , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Gregory CHEN , Van LE , Amrita MATHURIYA , Abhishek SHARMA , Raghavan KUMAR , Phil KNAG , Huseyin SUMBUL
发明人： Jack KAVALIEROS , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Gregory CHEN , Van LE , Amrita MATHURIYA , Abhishek SHARMA , Raghavan KUMAR , Phil KNAG , Huseyin SUMBUL
IPC分类号： G06F13/16 , H01L25/18 , G11C11/419 , G11C11/408 , H01L23/522 , H03K19/21
摘要： Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.

3. 发明申请

US20190080731A1 MEMORY DEVICE WITH MULTIPLE MEMORY ARRAYS TO FACILITATE IN-MEMORY COMPUTATION 审中-公开
公开(公告)号：US20190080731A1
公开(公告)日：2019-03-14
申请号：US16124068
申请日：2018-09-06
申请人： Jack KAVALIEROS , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Gregory CHEN , Van LE , Amrita MATHURIYA , Abhishek SHARMA , Raghavan KUMAR , Phil KNAG , Huseyin SUMBUL
发明人： Jack KAVALIEROS , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Gregory CHEN , Van LE , Amrita MATHURIYA , Abhishek SHARMA , Raghavan KUMAR , Phil KNAG , Huseyin SUMBUL
IPC分类号： G11C7/10 , G11C11/56 , G11C7/18
摘要： Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.

4. 发明申请

US20200098824A1 DIODE BASED RESISTIVE RANDOM ACCESS MEMORY 审中-公开
公开(公告)号：US20200098824A1
公开(公告)日：2020-03-26
申请号：US16142040
申请日：2018-09-26
申请人： Abhishek SHARMA , Gregory K. CHEN , Ram KRISHNAMURTHY , Ravi PILLARISETTY , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Raghavan KUMAR , Phil KNAG , Huseyin SUMBUL , Urusa ALAAN , Noriyuki SATO
发明人： Abhishek SHARMA , Gregory K. CHEN , Ram KRISHNAMURTHY , Ravi PILLARISETTY , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Raghavan KUMAR , Phil KNAG , Huseyin SUMBUL , Urusa ALAAN , Noriyuki SATO
IPC分类号： H01L27/24 , H01L45/00
摘要： Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a substrate, a RRAM storage cell above the substrate, and a diode adjacent to the RRAM storage cell. The RRAM storage cell includes a first electrode located in a first metal layer above the substrate, a resistive switching material layer adjacent to the first electrode, and a second electrode adjacent to the resistive switching material layer. The second electrode is shared between the RRAM storage cell and the diode. The diode includes the second electrode shared with the RRAM storage cell, a semiconductor layer adjacent to the second electrode, and a third electrode located in a second metal layer above the substrate. Other embodiments may be described and/or claimed.

5. 发明申请

US20190103156A1 FULL-RAIL DIGITAL READ COMPUTE-IN-MEMORY CIRCUIT 审中-公开
公开(公告)号：US20190103156A1
公开(公告)日：2019-04-04
申请号：US16146932
申请日：2018-09-28
申请人： Huseyin Ekin SUMBUL , Gregory K. CHEN , Raghavan KUMAR , Phil Ekin KNAG , Abhishek SHARMA , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Ram A. KRISHNAMURTHY , Ian A. YOUNG
发明人： Huseyin Ekin SUMBUL , Gregory K. CHEN , Raghavan KUMAR , Phil Ekin KNAG , Abhishek SHARMA , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Ram A. KRISHNAMURTHY , Ian A. YOUNG
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/1006 , G11C7/12 , G11C11/412 , G11C11/418 , G11C27/024
摘要： A full-rail digital-read CIM circuit enables a weighted read operation on a single row of a memory array. A weighted read operation captures a value of a weight stored in the single memory array row without having to rely on weighted row-access. Rather, using full-rail access and a weighted sampling capacitance network, the CIM circuit enables the weighted read operation even under process variation, noise and mismatch.

6. 发明申请

US20200098887A1 CONTACT ELECTRODES AND DIELECTRIC STRUCTURES FOR THIN FILM TRANSISTORS 审中-公开
公开(公告)号：US20200098887A1
公开(公告)日：2020-03-26
申请号：US16143326
申请日：2018-09-26
申请人： Gilbert DEWEY , Van H. LE , Abhishek SHARMA , Jack T. KAVALIEROS , Sean MA , Seung Hoon SUNG , Nazila HARATIPOUR , Tahir GHANI , Justin WEBER , Shriram SHIVARAMAN
发明人： Gilbert DEWEY , Van H. LE , Abhishek SHARMA , Jack T. KAVALIEROS , Sean MA , Seung Hoon SUNG , Nazila HARATIPOUR , Tahir GHANI , Justin WEBER , Shriram SHIVARAMAN
IPC分类号： H01L29/51 , H01L29/786 , H01L29/49 , H01L29/417 , H01L27/088 , H01L29/66
摘要： Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.

7. 发明申请

US20200098932A1 MEMORY CELLS BASED ON THIN-FILM TRANSISTORS 审中-公开
公开(公告)号：US20200098932A1
公开(公告)日：2020-03-26
申请号：US16142300
申请日：2018-09-26
申请人： Travis W. LAJOIE , Abhishek SHARMA , Van H. LE , Chieh-Jen KU , Pei-Hua WANG , Jack T. KAVALIEROS , Bernhard SELL , Tahir GHANI , Juan ALZATE VINASCO
发明人： Travis W. LAJOIE , Abhishek SHARMA , Van H. LE , Chieh-Jen KU , Pei-Hua WANG , Jack T. KAVALIEROS , Bernhard SELL , Tahir GHANI , Juan ALZATE VINASCO
IPC分类号： H01L29/786 , H01L29/49 , H01L29/66 , H01L27/108
摘要： Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

8. 发明申请

US20200091274A1 NON-LINEAR GATE DIELECTRIC MATERIAL FOR THIN-FILM TRANSISTORS 审中-公开
公开(公告)号：US20200091274A1
公开(公告)日：2020-03-19
申请号：US16134876
申请日：2018-09-18
申请人： Abhishek SHARMA , Ravi PILLARISETTY , Brian DOYLE , Elijah KARPOV , Prashant MAJHI , Gilbert DEWEY , Benjamin CHU-KUNG , Van H. LE , Jack T. KAVALIEROS , Tahir GHANI
发明人： Abhishek SHARMA , Ravi PILLARISETTY , Brian DOYLE , Elijah KARPOV , Prashant MAJHI , Gilbert DEWEY , Benjamin CHU-KUNG , Van H. LE , Jack T. KAVALIEROS , Tahir GHANI
IPC分类号： H01L49/02 , H01L29/51 , H01L29/66
摘要： Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a gate dielectric layer adjacent to the channel layer, and a gate electrode separated from the channel layer by the gate dielectric layer. The gate dielectric layer includes a non-linear gate dielectric material. The gate electrode, the channel layer, and the gate dielectric layer form a non-linear capacitor. Other embodiments may be described and/or claimed.

9. 发明申请

US20110055121A1 SYSTEM AND METHOD FOR IDENTIFYING AN OBSERVED PHENEMENON 审中-公开
标题翻译：用于识别观察到的菲涅耳的系统和方法
公开(公告)号：US20110055121A1
公开(公告)日：2011-03-03
申请号：US12240796
申请日：2008-09-29
申请人： Ankur Datta , Kevin Myungho Yoon , Sajid Mahmood Siddiqi , Michael Scott Bauer , Abhishek SHARMA
发明人： Ankur Datta , Kevin Myungho Yoon , Sajid Mahmood Siddiqi , Michael Scott Bauer , Abhishek SHARMA
IPC分类号： G06N5/02 , G06F15/18
CPC分类号： G06K9/6217 , G06F19/3418 , G06K9/6263 , G06N7/005 , G06N20/00
摘要： A system for identifying an observed phenomenon. The system includes a computing device configured for receiving disparate data streams associated with disparate data sources. The system also includes a feature extraction module communicably connected to the computing device, a classification module communicably connected to the computing device, and a consensus module communicably connected to the computing device. The feature extraction module is configured for generating a set of attributes for each data stream. The classification module is configured for soft associating labels with attributes for each set of attributes, and for generating a confidence value for each soft association. The consensus module is configured for generating an output indicative of the phenomenon. The consensus module includes a standardization module and a sequential data module. The standardization module is configured for standardizing the confidence values. The sequential data module is configured for generating the output based on the standardized confidence values.
摘要翻译：用于识别观察到的现象的系统。该系统包括被配置为接收与不同数据源相关联的不同数据流的计算设备。该系统还包括可通信地连接到计算设备的特征提取模块，可通信地连接到计算设备的分类模块，以及可通信地连接到计算设备的共识模块。特征提取模块被配置用于为每个数据流生成一组属性。分类模块被配置用于将标签与每个属性集合的属性进行软关联，并为每个软关联生成置信度值。共识模块被配置用于产生指示该现象的输出。共识模块包括标准化模块和顺序数据模块。标准化模块被配置为标准化置信度值。顺序数据模块被配置为基于标准化置信度值来生成输出。

10. 发明申请

US20200098931A1 VERTICAL THIN-FILM TRANSISTORS BETWEEN METAL LAYERS 审中-公开
公开(公告)号：US20200098931A1
公开(公告)日：2020-03-26
申请号：US16142075
申请日：2018-09-26
申请人： Abhishek SHARMA , Nazila HARATIPOUR , Seung Hoon SUNG , Benjamin CHU-KUNG , Gilbert DEWEY , Shriram SHIVARAMAN , Van H. LE , Jack T. KAVALIEROS , Tahir GHANI , Matthew V. METZ , Arnab SEN GUPTA
发明人： Abhishek SHARMA , Nazila HARATIPOUR , Seung Hoon SUNG , Benjamin CHU-KUNG , Gilbert DEWEY , Shriram SHIVARAMAN , Van H. LE , Jack T. KAVALIEROS , Tahir GHANI , Matthew V. METZ , Arnab SEN GUPTA
IPC分类号： H01L29/786 , H01L29/49 , H01L29/66 , H01L27/24 , H01L27/108
摘要： Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a first metal electrode located in a first metal layer is coupled to a first portion of the channel layer by a first short via, and a second metal electrode located in a second metal layer is coupled to a second portion of the channel layer by a second short via. Other embodiments may be described and/or claimed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式