专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09870640B2 Techniques and architecture for improved vertex processing 有权
公开(公告)号：US09870640B2
公开(公告)日：2018-01-16
申请号：US14961755
申请日：2015-12-07
申请人： Intel Corporation
发明人： Rahul P. Sathe , Tim Foley
IPC分类号： G09G5/36 , G06T1/60 , G06T15/00
CPC分类号： G06T15/005 , G06T1/60 , G06T2200/28
摘要： An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.

2. 发明授权

US09626795B2 Reducing shading by merging fragments from the adjacent primitives 有权
公开(公告)号：US09626795B2
公开(公告)日：2017-04-18
申请号：US14108419
申请日：2013-12-17
申请人： Intel Corporation
发明人： Rahul P. Sathe
IPC分类号： G06T15/50 , G06T15/80 , G06T17/20
CPC分类号： G06T17/20 , G06T15/005 , G06T15/80
摘要： Instead of shading a triangle from the rasterizer as soon as it is known that there is a sample inside the triangle, in accordance with one embodiment, shading is delayed until the triangle beside it, called the neighboring triangle, is received. If there is a neighboring triangle facing the same way, with non-mutually exclusive coverage, meaning that it is not overlapping the same region, then the shader shades only once for the pair of triangles. That is, two separate fragments are merged and treated as one fragment. Specifically, the fragment that is over the pixel center is the one that is used and the other fragment is replaced by merging. The merger happens only over the extent of a pixel and more than one primitive is not shaded at a time. However, multiple merges within a 2×2 block of pixels are possible.

3. 发明授权

US10636110B2 Architecture for interleaved rasterization and pixel shading for virtual reality and multi-view systems 有权
公开(公告)号：US10636110B2
公开(公告)日：2020-04-28
申请号：US15195005
申请日：2016-06-28
申请人： Intel Corporation
发明人： Rahul P. Sathe
IPC分类号： G06T1/60
CPC分类号： G06T1/60
摘要： One embodiment provides for a graphics processing apparatus comprising first logic to rasterize pixel regions associated with multiple interleaved primitives; second logic to shade pixel regions covered by one or more of the multiple interleaved primitives; and third logic to interleave output of the second logic for the multiple interleaved primitives to a single render target, the single render target including output associated with the multiple interleaved primitives.

4. 发明授权

US10262455B2 Merging fragments for coarse pixel shading using a weighted average of the attributes of triangles 有权
公开(公告)号：US10262455B2
公开(公告)日：2019-04-16
申请号：US14959185
申请日：2015-12-04
申请人： Intel Corporation
发明人： Gabor Liktor , Marco Salvi , Rahul P. Sathe
IPC分类号： G09G5/36 , G06T11/40 , G06T15/00 , G06T15/50 , G06T15/80 , G06T17/20
摘要： Two primitives may be merged by interpolating vertex attributes at coarse pixel centers. Input attributes are computed as a coverage weighted average of the interpolated vertex attributes. Then coarse pixel shading is performed using the merged primitives.

5. 发明授权

US09934606B2 Deferred coarse pixel shading 有权
公开(公告)号：US09934606B2
公开(公告)日：2018-04-03
申请号：US14487432
申请日：2014-09-16
申请人： Intel Corporation
发明人： Rahul P. Sathe , Marco Salvi
IPC分类号： G06T15/80 , G06T15/00 , G09G5/36
CPC分类号： G06T15/80 , G06T15/005 , G09G5/363 , G09G2350/00 , G09G2360/08 , G09G2360/121
摘要： A shading rate may be set by analyzing samples within a pixel. Then based on that analysis, a system determines whether to use coarse pixel, pixel or sample shading for a region of pixels. Based on the determined type of shading, the shading rate may be set.

6. 发明授权

US10242419B2 Compiler optimization to reduce the control flow divergence 有权
公开(公告)号：US10242419B2
公开(公告)日：2019-03-26
申请号：US14843698
申请日：2015-09-02
申请人： INTEL CORPORATION
发明人： Rahul P. Sathe
IPC分类号： G06T1/20 , G06T1/60
摘要： In one embodiment a graphics processing system comprises a graphics processor having execution logic and shared memory and a shader compiler unit to compile a shader program for execution by the execution logic of the graphic processor, wherein the shader is to optimize the shader program during the compile, wherein to optimize the shader program includes to convert a divergent block of parallel instructions into a divergent block and a non-divergent block of instructions.

7. 发明授权

US09916682B2 Variable precision shading 有权
公开(公告)号：US09916682B2
公开(公告)日：2018-03-13
申请号：US14925325
申请日：2015-10-28
申请人： Intel Corporation
发明人： Rahul P. Sathe , Bimal Poddar , Jon N. Hasselgren
IPC分类号： G06T15/80 , G06K9/46 , G06T15/00 , G06T15/04
CPC分类号： G06T15/80 , G06K9/4604 , G06K9/4671 , G06K2009/4666 , G06T15/005 , G06T15/04 , G06T2200/04 , G06T2200/28 , G06T2210/36 , G06T2215/16
摘要： The power consumption of processor-based devices may be reduced by reducing the consumption of power during graphics processing. In some embodiments, the precision of pixel shading in parts of images where artifacts are less objectionable may be reduced. For example, in areas the user is not directly looking at, precision may be reduced to save power. At the same time, because a person is not focusing on those regions, even if usually perceptible artifacts occur because of the reduced precision, an overall pleasing depiction may be achieved.

8. 发明申请

US20170132833A1 PROGRAMMABLE PER PIXEL SAMPLE PLACEMENT USING CONSERVATIVE RASTERIZATION 审中-公开
公开(公告)号：US20170132833A1
公开(公告)日：2017-05-11
申请号：US14937438
申请日：2015-11-10
申请人： INTEL CORPORATION
发明人： Rahul P. Sathe
IPC分类号： G06T15/80 , G06T15/04 , G06T1/20
CPC分类号： G06T15/80 , G06T1/20 , G06T11/40 , G06T15/005 , G06T15/04
摘要： A graphics processing apparatus comprising a graphics processing pipeline including shader execution logic to execute shading instructions. The shading instructions causes the shader execution logic to programmatically determine a sample location for multiple pixels within a frame. The sample locations are determined based on a location of the pixel within the frame and can be determined by shader logic provided to the graphic processing apparatus by a graphics application.

9. 发明授权

US09449419B2 Post tessellation edge cache 有权
标题翻译：贴图边缘缓存
公开(公告)号：US09449419B2
公开(公告)日：2016-09-20
申请号：US13628247
申请日：2012-09-27
申请人： Intel Corporation
发明人： Rahul P. Sathe , Tim Foley , Karthik Vaidyanathan
IPC分类号： G06F12/02 , G06T15/00 , G06T1/60 , G06T17/20
CPC分类号： G06T15/005 , G06T1/60 , G06T17/20
摘要： In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.
摘要翻译：根据一些实施例，当它们是冗余时，可以消除域着色器和/或细分器操作。通过使用角落缓存，检查可以确定在域着色器和/或细分器中是否已经评估了一个给定的角点（无论是顶点还是四边形角），如果是，则可以重新使用先前操作的结果执行可能增加功耗或降低速度的不必要的调用。

10. 发明授权

US09208602B2 Techniques and architecture for improved vertex processing 有权
标题翻译：改进顶点处理技术和架构
公开(公告)号：US09208602B2
公开(公告)日：2015-12-08
申请号：US14039732
申请日：2013-09-27
申请人： Intel Corporation
发明人： Rahul P. Sathe , Tim Foley
IPC分类号： G09G5/36 , G06T1/60 , G06T15/00
CPC分类号： G06T15/005 , G06T1/60 , G06T2200/28
摘要： An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.
摘要翻译：设备可以包括索引缓冲器，用于存储索引流，该索引流具有对应于网格顶点和顶点高速缓存的多个索引条目，以存储网格的多个经处理的顶点。该装置还可以包括处理器电路和顶点管理器，用于在处理器电路上执行以读取包括多个比特流条目的参考比特流，每个比特流条目对应于索引流的索引条目，并且移除经处理的顶点当与所处理的顶点相对应的参考比特流条目的值等于定义的值时，从顶点高速缓存。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式