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1. 发明授权

US11531542B2 Addition instructions with independent carry chains 有权
公开(公告)号：US11531542B2
公开(公告)日：2022-12-20
申请号：US17393361
申请日：2021-08-03
申请人： Intel Corporation
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret L. Toll
IPC分类号： G06F9/30 , G06F9/38
摘要： A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

2. 发明授权

US10911222B2 Instructions processors, methods, and systems to process secure hash algorithms 有权
公开(公告)号：US10911222B2
公开(公告)日：2021-02-02
申请号：US16807021
申请日：2020-03-02
申请人： Intel Corporation
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford
IPC分类号： H04L9/06 , G06F21/64 , G06F9/30 , G06F21/72 , G06F21/60
摘要： A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.

3. 发明授权

US10725779B2 Method and apparatus to process SHA-2 secure hashing algorithm 有权
公开(公告)号：US10725779B2
公开(公告)日：2020-07-28
申请号：US16450319
申请日：2019-06-24
申请人： Intel Corporation
发明人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F9/30 , G06F21/60 , G06F12/0875 , G06F12/1027 , G09C1/00 , H04L9/32 , G06F9/38 , G06F12/0897 , G06F13/28 , G06F13/40 , G06F13/42 , G06F15/80 , H04L9/06
摘要： A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

4. 发明授权

US10509580B2 Memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match 有权
公开(公告)号：US10509580B2
公开(公告)日：2019-12-17
申请号：US15089456
申请日：2016-04-01
申请人： Intel Corporation
发明人： Kirk S. Yap , Vinodh Gopal , James D. Guilford , Sean M. Gulley
IPC分类号： G06F3/06 , G06F12/00 , H03M7/30
摘要： Methods and apparatuses relating to memory compression and decompression are described, including a memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match. When indices for multiple sections are the same, an entry in the dictionary may be updated with the value of the section that is most recent, in the same order as in the block of data. In one embodiment, a hardware compression engine is to determine when each section of a plurality of sections of a block of data is a zero value, a full match or a partial match to an entry in a dictionary, or a no match to any entry in the dictionary, encode a tag for each section to indicate the one of the zero value, the full match, the partial match, and the no match, encode a literal when the section is the no match, an index to the entry in the dictionary when the section is the full match, and an index to the entry in the dictionary and non-matching bits when the section is the partial match, and update an entry in the dictionary with a value of a section when the section is the no match, wherein tags for the plurality of sections are to be output from the hardware compression engine in a single field, literals for the plurality of sections are to be output from the hardware compression engine in a single field, indexes for the plurality of sections are to be output from the hardware compression engine in a single field, and non-matching bits for the plurality of sections are to be output from the hardware compression engine in a single field. A hash value may be generated for each of a plurality of sections of a block of data to use as an index in a dictionary.

5. 发明申请

US20190363733A1 METHODS AND APPARATUS TO PARALLELIZE DATA DECOMPRESSION 审中-公开
公开(公告)号：US20190363733A1
公开(公告)日：2019-11-28
申请号：US16402845
申请日：2019-05-03
申请人： Intel Corporation
发明人： Vinodh Gopal , James D. Guilford , Sudhir K. Satpathy , Sanu K. Mathew
IPC分类号： H03M7/30 , H03M7/40
摘要： Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.

6. 发明授权

US10198248B2 Parallel processing of a single data buffer 有权
公开(公告)号：US10198248B2
公开(公告)日：2019-02-05
申请号：US13631761
申请日：2012-09-28
申请人： Intel Corporation
发明人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
IPC分类号： G06F5/06 , G06F21/64 , H04L9/06 , H04L9/32
摘要： Technologies for executing a serial data processing algorithm on a single variable length data buffer includes streaming segments of the buffer into a data register, executing the algorithm on each of the segments in parallel, and combining the results of executing the algorithm on each of the segments to form the output of the serial data processing algorithm.

7. 发明授权

US10177782B2 Hardware apparatuses and methods for data decompression 有权
公开(公告)号：US10177782B2
公开(公告)日：2019-01-08
申请号：US14757854
申请日：2015-12-26
申请人： Intel Corporation
发明人： Sudhir K. Satpathy , James D. Guilford , Sanu K. Mathew , Vinodh Gopal , Vikram B. Suresh
IPC分类号： H03M7/30 , H03M7/40 , G06F9/38 , G06F9/46
摘要： Methods and apparatuses relating to data decompression are described. In one embodiment, a hardware processor includes a core to execute a thread and offload a decompression thread for an encoded, compressed data stream comprising a literal code, a length code, and a distance code, and a hardware decompression accelerator to execute the decompression thread to selectively provide the encoded, compressed data stream to a first circuit to serially decode the literal code to a literal symbol, serially decode the length code to a length symbol, and serially decode the distance code to a distance symbol, and selectively provide the encoded, compressed data stream to a second circuit to look up the literal symbol for the literal code from a table, look up the length symbol for the length code from the table, and look up the distance symbol for the distance code from the table.

8. 发明申请

US20180152202A1 TECHNOLOGIES FOR A HIGH-RATIO COMPRESSION ACCELERATOR WITH HETEROGENEOUS HISTORY BUFFERS 审中-公开
公开(公告)号：US20180152202A1
公开(公告)日：2018-05-31
申请号：US15720162
申请日：2017-09-29
申请人： Intel Corporation
发明人： Vinodh Gopal , James D. Guilford
IPC分类号： H03M7/30 , H03M7/40
CPC分类号： G06F3/0641 , G06F3/0604 , G06F3/0608 , G06F3/0611 , G06F3/0613 , G06F3/0617 , G06F3/0647 , G06F3/065 , G06F3/0653 , G06F3/067 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/3851 , G06F9/3891 , G06F9/4401 , G06F9/4881 , G06F9/5038 , G06F9/505 , G06F9/544 , G06F11/0709 , G06F11/0751 , G06F11/079 , G06F11/1453 , G06F11/3006 , G06F11/3034 , G06F11/3055 , G06F11/3409 , G06F12/023 , G06F12/0284 , G06F12/0692 , G06F13/1652 , G06F15/80 , G06F16/1744 , G06F21/57 , G06F21/6218 , G06F21/73 , G06F21/76 , G06F2212/401 , G06F2212/402 , G06F2221/2107 , G06T1/20 , G06T1/60 , G06T9/005 , H01R13/4538 , H01R13/631 , H03K19/1731 , H03M7/3084 , H03M7/40 , H03M7/42 , H03M7/60 , H03M7/6011 , H03M7/6017 , H03M7/6029 , H04L9/0822 , H04L12/2881 , H04L12/4633 , H04L41/044 , H04L41/046 , H04L41/0816 , H04L41/0853 , H04L41/0896 , H04L41/12 , H04L41/142 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L47/78 , H04L49/104 , H04L61/2007 , H04L63/1425 , H04L67/10 , H04L67/1014 , H04L67/327 , H04L67/36 , H05K7/1452 , H05K7/1487
摘要： Technologies for high-ratio compression with heterogeneous history buffers include a computing device having an accelerator complex with a large history buffer and a small history buffer. The large history buffer has a larger size than the small history buffer. For example, the small history buffer may be 32 kilobytes and the large history buffer may be 64 kilobytes, 1 megabyte, or larger. The large history buffer is coupled to a large-buffer compare core that searches for matches in the large history buffer, finds a best match, and forwards the best match to a small-buffer compare core. The small-buffer compare core searches the small history buffer for matches, receives the match forwarded from the large-buffer compare core, and determines a best match from the matches in the small history buffer and the forwarded match. Other embodiments are described and claimed.

9. 发明授权

US09929747B2 Technologies for high-performance single-stream LZ77 compression 有权
公开(公告)号：US09929747B2
公开(公告)日：2018-03-27
申请号：US15395702
申请日：2016-12-30
申请人： Intel Corporation
发明人： Vinodh Gopal , James D. Guilford , Daniel F. Cutter , Kirk S. Yap
IPC分类号： H03M7/38 , H03M7/40 , H04L29/06 , H03M7/30
CPC分类号： H04Q11/0005 , B25J15/0014 , B65G1/0492 , G02B6/3882 , G02B6/3893 , G02B6/3897 , G02B6/4292 , G02B6/4452 , G05D23/1921 , G05D23/2039 , G06F1/183 , G06F3/061 , G06F3/0611 , G06F3/0616 , G06F3/0619 , G06F3/0625 , G06F3/0631 , G06F3/0638 , G06F3/064 , G06F3/0647 , G06F3/0653 , G06F3/0658 , G06F3/0659 , G06F3/0664 , G06F3/0665 , G06F3/067 , G06F3/0673 , G06F3/0679 , G06F3/0683 , G06F3/0688 , G06F3/0689 , G06F8/65 , G06F9/4401 , G06F9/5016 , G06F9/5044 , G06F9/505 , G06F9/5072 , G06F9/5077 , G06F11/141 , G06F11/3414 , G06F12/0862 , G06F12/0893 , G06F12/10 , G06F12/109 , G06F12/1408 , G06F13/161 , G06F13/1668 , G06F13/1694 , G06F13/4022 , G06F13/4068 , G06F13/409 , G06F13/42 , G06F13/4282 , G06F15/8061 , G06F17/30949 , G06F2209/5019 , G06F2209/5022 , G06F2212/1008 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/152 , G06F2212/202 , G06F2212/401 , G06F2212/402 , G06F2212/7207 , G06Q10/06 , G06Q10/06314 , G06Q10/087 , G06Q10/20 , G06Q50/04 , G07C5/008 , G08C17/02 , G08C2200/00 , G11C5/02 , G11C5/06 , G11C7/1072 , G11C11/56 , G11C14/0009 , H03M7/30 , H03M7/3084 , H03M7/3086 , H03M7/40 , H03M7/4031 , H03M7/4056 , H03M7/4081 , H03M7/6005 , H03M7/6023 , H04B10/25 , H04B10/2504 , H04L9/0643 , H04L9/14 , H04L9/3247 , H04L9/3263 , H04L12/2809 , H04L29/12009 , H04L41/024 , H04L41/046 , H04L41/0813 , H04L41/082 , H04L41/0896 , H04L41/12 , H04L41/145 , H04L41/147 , H04L41/5019 , H04L43/065 , H04L43/08 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L43/16 , H04L45/02 , H04L45/52 , H04L47/24 , H04L47/765 , H04L47/782 , H04L47/805 , H04L47/82 , H04L47/823 , H04L49/15 , H04L49/25 , H04L49/357 , H04L49/45 , H04L49/555 , H04L67/02 , H04L67/10 , H04L67/1004 , H04L67/1008 , H04L67/1012 , H04L67/1014 , H04L67/1029 , H04L67/1034 , H04L67/1097 , H04L67/12 , H04L67/16 , H04L67/306 , H04L67/34 , H04L69/04 , H04L69/329 , H04Q1/04 , H04Q11/00 , H04Q11/0003 , H04Q11/0062 , H04Q11/0071 , H04Q2011/0037 , H04Q2011/0041 , H04Q2011/0052 , H04Q2011/0073 , H04Q2011/0079 , H04Q2011/0086 , H04Q2213/13523 , H04Q2213/13527 , H04W4/023 , H04W4/80 , H05K1/0203 , H05K1/181 , H05K5/0204 , H05K7/1418 , H05K7/1421 , H05K7/1422 , H05K7/1447 , H05K7/1461 , H05K7/1485 , H05K7/1487 , H05K7/1489 , H05K7/1491 , H05K7/1492 , H05K7/1498 , H05K7/2039 , H05K7/20709 , H05K7/20727 , H05K7/20736 , H05K7/20745 , H05K7/20836 , H05K13/0486 , H05K2201/066 , H05K2201/10121 , H05K2201/10159 , H05K2201/10189 , Y10S901/01
摘要： Technologies for high-performance single-stream data compression include a computing device that updates an index data structure based on an input data stream. The input data stream is divided into multiple chunks. Each chunk has a predetermined length, such as 136 bytes, and overlaps the previous chunk by a predetermine amount, such as eight bytes. The computing device processes multiple chunks in parallel using the index data to generate multiple token streams. The tokens include literal tokens and reference tokens that refer to matching data from earlier in the input data stream. The computing device thus searches for matching data in parallel. The computing device merges the token streams to generate a single output token stream. The computing device may merge a pair of tokens from two different chunks to generate one or more synchronized tokens that are output to the output token stream. Other embodiments are described and claimed.

10. 发明授权

US09917597B1 Method and apparatus for accelerated data compression with hints and filtering 有权
公开(公告)号：US09917597B1
公开(公告)日：2018-03-13
申请号：US15382031
申请日：2016-12-16
申请人： Intel Corporation
发明人： Daniel F. Cutter , Vinodh Gopal , James D. Guilford
IPC分类号： H03M7/30 , H04L29/06
CPC分类号： H03M7/3086 , H03M7/30 , H03M7/6029
摘要： A processor includes a decoder to decode an instruction to compress an input data stream and an execution unit for executing the instruction. The execution unit to generate metadata for a current input of the input data stream, the metadata comprises a first hint based on a portion of a current input that represents the input data stream at a current offset, select a first pointer to identify a location in a history buffer in a hash chain, determine whether the metadata generated for the current input matches metadata previously generated for the first pointer, and filter the first pointer from a search for a best match for the current input in the history buffer based on the determination that at least a portion of the metadata for the current input does not match a portion of the metadata for the first pointer.

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