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1. 发明申请

US20210272916A1 INTEGRATED CIRCUIT 有权
公开(公告)号：US20210272916A1
公开(公告)日：2021-09-02
申请号：US17163597
申请日：2021-02-01
申请人： Infineon Technologies AG
发明人： Thomas KUENEMUND , Markus GRUETZNER , Peter EGGER
IPC分类号： H01L23/00 , H03K19/003 , H01L27/02 , H01L27/092
摘要： Various embodiments describe an integrated circuit. The integrated circuit includes at least seven planar field effect transistors provided in a common substrate next to one another with a maximum feature size in accordance with a technology node of a maximum of 65 nm. Each field effect transistor of the at least seven planar field effect transistors includes a first source/drain diffusion region, a second source/drain diffusion region, a channel region between the drain diffusion region and the source diffusion region, and a gate terminal. Each field effect transistor of the at least seven planar field effect transistors includes at least one common source/drain diffusion region with another field effect transistor of the at least seven planar field effect transistors. The common source/drain diffusion regions are free of vertical terminal contact material.

2. 发明申请

US20150135340A1 CIRCUIT ARRANGEMENT AND METHOD FOR SAFEGUARDING A CIRCUIT ARRANGEMENT WITH RESPECT TO REPEATED LIGHT ATTACKS 有权
标题翻译：电路布置及保护电路布置的方法
公开(公告)号：US20150135340A1
公开(公告)日：2015-05-14
申请号：US14541258
申请日：2014-11-14
申请人： Infineon Technologies AG
发明人： Uwe WEDER , Thomas KUENEMUND
IPC分类号： G06F21/76
CPC分类号： G06F21/75 , G06F21/556 , G06F21/755 , G06F21/76 , H01L23/552 , H01L23/576
摘要： In various embodiments, a circuit arrangement is provided. The circuit arrangement may include a detection circuit, which is designed to detect light attacks on the circuit arrangement; a processing circuit, which is designed to initiate a current flow through a line for each light attack detected by the detection circuit; and a control circuit, which is designed to enable functioning of a component of the circuit arrangement depending on the conducting state of the line.
摘要翻译：在各种实施例中，提供电路装置。电路装置可以包括检测电路，其被设计为检测对电路装置的光线攻击; 处理电路，其被设计为启动由检测电路检测到的每个光攻击的线路的电流; 以及控制电路，其被设计成根据线路的导通状态使得电路装置的部件能够起作用。

3. 发明申请

US20210257363A1 CHIP AND METHOD FOR MANUFACTURING A CHIP 有权
公开(公告)号：US20210257363A1
公开(公告)日：2021-08-19
申请号：US17176196
申请日：2021-02-16
申请人： Infineon Technologies AG
发明人： Thomas KUENEMUND
IPC分类号： H01L27/092 , H01L29/08 , H01L29/417 , H01L29/40 , H01L21/8238 , H01L27/02
摘要： A chip is described including a semiconductor layer including doped regions; a metallization layer on the semiconductor layer and at least one cell row including p-channel field effect transistors and n-channel field effect transistors, wherein the doped regions form source regions and drain regions of the p-channel field effect transistors and the n-channel field effect transistors; contacts extending from the source regions, the drain regions and gate regions of the p-channel field effect transistors and the n-channel field effect transistors to the metallization layer, wherein the metallization layer is structured in accordance with a metallization grid such that the p-channel field effect transistors and the n-channel field effect transistors are connected to form one or more logic gates.

4. 发明申请

US20150067012A1 METHOD AND DATA PROCESSING DEVICE FOR RECONSTRUCTING A VECTOR 有权
标题翻译：用于重建矢量的方法和数据处理装置
公开(公告)号：US20150067012A1
公开(公告)日：2015-03-05
申请号：US14470953
申请日：2014-08-28
申请人： INFINEON TECHNOLOGIES AG
发明人： Rainer GOETTFERT , Berndt GAMMEL , Thomas KUENEMUND
IPC分类号： G06F17/16
CPC分类号： G06F17/16 , G06F7/588 , H04L9/0866 , H04L2209/34
摘要： A method for reconstructing a first vector from a second vector includes: storing code for the row vectors according to a first code and a second code; correcting the row vectors of the second vector corresponding to the first vector so that the row vectors of the second vector have the same code as the row vectors of the first vector; calculating the code of the column vectors of the second vector according to the second code; comparing the code of the row vectors of the second vector with the code of the column vectors of the first vector; identifying the columns in which the first vector is unequal to the second vector; the rows in which the first vector is unequal to the second vector; and the components in which the first vector is not equal to the second vector, and correcting the components of the second vector.
摘要翻译：一种从第二矢量重构第一矢量的方法包括：根据第一码和第二码存储行向量的码; 对与第一向量相对应的第二向量的行向量进行校正，使得第二向量的行向量具有与第一向量的行向量相同的代码; 根据第二代码计算第二向量的列向量的代码; 将第二向量的行向量的代码与第一向量的列向量的代码进行比较; 识别第一个向量不等于第二个向量的列; 第一个向量不等于第二个向量的行; 以及其中第一矢量不等于第二矢量的分量，以及校正第二矢量的分量。

5. 发明申请

US20180091149A1 CIRCUIT AND METHOD FOR CHECKING THE INTEGRITY OF A CONTROL SIGNAL 有权
公开(公告)号：US20180091149A1
公开(公告)日：2018-03-29
申请号：US15718033
申请日：2017-09-28
申请人： Infineon Technologies AG
发明人： Thomas KUENEMUND , Molka BEN ROMDHANE , Berndt GAMMEL
IPC分类号： H03K19/007 , H03K3/3562
CPC分类号： H03K19/007 , H03K3/0372 , H03K3/0375 , H03K3/3562
摘要： According to an embodiment, a circuit is described comprising a plurality of flip-flops, a control circuit configured to provide a control signal to each flip-flop of the plurality of flip-flops and an integrity checking circuit connected to the control circuit and to the plurality of flip-flops configured to check whether the flip-flops receive the control signal as provided by the control circuit.

6. 发明申请

US20160241239A1 SEMICONDUCTOR CHIP 审中-公开
公开(公告)号：US20160241239A1
公开(公告)日：2016-08-18
申请号：US15135610
申请日：2016-04-22
申请人： Infineon Technologies AG
发明人： Thomas KUENEMUND
IPC分类号： H03K19/003 , H03K19/0948 , H03K19/21 , H01L23/00 , H01L27/092
CPC分类号： H01L27/092 , H01L23/528 , H01L23/576 , H01L2924/0002 , H03K19/00315 , H03K19/0948 , H03K19/215 , H01L2924/00
摘要： According to one embodiment, a chip has a circuit with at least one p channel field effect transistor (FET); at least one n channel FET; a first and a second power supply terminal; wherein the n channel FET, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the p channel FET; and the p channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the n channel FET; wherein the logic state of the gate of the p channel FET and of the n channel FET can only be changed by at least one of the first and second supply voltage to the circuit; and a connection coupled to the gate of the p channel FET or the n channel FET and a further component of the semiconductor chip.

7. 发明申请

US20210280536A1 INTEGRATED CIRCUIT 有权
公开(公告)号：US20210280536A1
公开(公告)日：2021-09-09
申请号：US17183396
申请日：2021-02-24
申请人： Infineon Technologies AG
发明人： Thomas KUENEMUND
IPC分类号： H01L23/00 , H03K19/003 , G06F21/72 , H03K19/094
摘要： According to various embodiments, an integrated circuit is described comprising a plurality of subcircuits having different signal transfer reaction times, a control circuit configured to form two competing paths from the plurality of subcircuits in response to a control signal, an input circuit configured to supply an input signal to the two competing paths and an output circuit configured to generate an output value depending on which of the competing paths has transferred the input signal with shorter reaction time.

8. 发明申请

US20190140643A1 DELAY CIRCUIT 审中-公开
公开(公告)号：US20190140643A1
公开(公告)日：2019-05-09
申请号：US16183827
申请日：2018-11-08
申请人： Infineon Technologies AG
发明人： Thomas KUENEMUND
IPC分类号： H03K19/003 , H03K17/00 , H04L9/32
摘要： A delay circuit includes an electronic transmission element with a first input and a first output. The first input is coupled to the first output by two first switches wired in parallel. The first switches each have a control input, a second input and a second output. The second input is coupled to the second output by two second switches wired in parallel. The circuit further includes an input circuit to receive an input signal and feed the input signal to one of the transmission element inputs and feed the inverted input signal to the other of the transmission element inputs, and an output circuit. The output circuit is configured such that the output signal only changes in the case of a change in the input signal if the change in the input signal has brought about a change both at the first output and at the second output.

9. 发明申请

US20180091155A1 PROGRAMMABLE LOGIC CIRCUIT AND METHOD FOR IMPLEMENTING A BOOLEAN FUNCTION 有权
公开(公告)号：US20180091155A1
公开(公告)日：2018-03-29
申请号：US15701478
申请日：2017-09-12
申请人： Infineon Technologies AG
发明人： Thomas KUENEMUND
IPC分类号： H03K19/177 , H03K19/173 , H03K19/003 , H03K19/0185 , H03K19/094 , H03K19/20
CPC分类号： H03K19/17708 , H03K19/00315 , H03K19/0185 , H03K19/094 , H03K19/1733 , H03K19/17768 , H03K19/20
摘要： According to an embodiment, a programmable logic circuit is described comprising a first data bit input to receive a first data bit a and a second data bit input to receive a second data bit b, a first program bit input to receive a first program bit p1, a second program bit input to receive a second program bit p2, a third program bit input to receive a third program bit p3 and a fourth program bit to receive a fourth program bit p4 and an output configured to output ( ( ( a ⋀ b ) ⋁ ( p 1 ⋀ a ) ⋁ ( p 2 ⋀ b ) ) _ ⋀ ( p 3 ⋁ b ⋁ a ) ) ⋁ ( a ⋀ b ⋀ p 4 ) _ .

10. 发明申请

US20170083723A1 ZERO DETECTION CIRCUIT AND MASKED BOOLEAN OR CIRCUIT 审中-公开
公开(公告)号：US20170083723A1
公开(公告)日：2017-03-23
申请号：US15272458
申请日：2016-09-22
申请人： Infineon Technologies AG
发明人： Franz KLUG , Thomas KUENEMUND
IPC分类号： G06F21/71
CPC分类号： G06F21/71 , G06F7/00 , G06F21/72 , G09C1/00 , H03K5/1536 , H03K5/22 , H04L9/004 , H04L2209/04
摘要： A zero detection circuit includes a chain of masked OR circuits. Each masked OR circuit includes data inputs. Each data input is configured to receive a respective data input bit. Each masked OR circuit further includes an input mask input to receive one or more input masking bits, an output mask input to receive an output masking bit and a data output. The zero detection circuit is configured to output a bit equal to an OR combination, masked with the output masking bit, of the data input bits, each demasked with an input masking bit of the one or more input masking bits. One of the inputs of each masked OR circuit except the first masked OR circuit of the chain of masked OR circuits is coupled to the data output of the masked OR circuit preceding the masked OR circuit in the chain of masked OR circuits.

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