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1. 发明授权

US10268519B2 Scheduling method and processing device for thread groups execution in a computing system 有权
公开(公告)号：US10268519B2
公开(公告)日：2019-04-23
申请号：US14983086
申请日：2015-12-29
申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
发明人： Heng-Yi Chen , Chung-Ho Chen , Chen-Chieh Wang , Juin-Ming Lu , Chun-Hung Lai , Hsun-Lun Huang
IPC分类号： G06F9/46 , G06F9/50
摘要： A scheduling method is provided. The method includes: recording a next instruction and a ready state of each thread group in a scoreboard; determining whether there is any ready thread group whose ready state is affirmative; determining whether a load/store unit is available, wherein the load/store unit is configured to access a data memory unit; when the load/store unit is available, determining whether the ready thread groups include a data access thread group, wherein the next instruction of the data access thread group is related to accessing the data memory unit; selecting a target thread group from the data access thread groups; and dispatching the target thread group to the load/store unit for execution.

2. 发明授权

US10412331B2 Power consumption estimation method and power consumption estimation apparatus 有权
公开(公告)号：US10412331B2
公开(公告)日：2019-09-10
申请号：US15853549
申请日：2017-12-22
申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
发明人： Chun Wei Chen , Ming-Der Shieh , Juin-Ming Lu , Hsun-Lun Huang , Yao-Hua Chen
IPC分类号： H04N5/369 , H04N5/232
摘要： A power consumption estimation method is applied to an image with N rows of pixels, and comprises a pixel estimation procedure comprising performing an estimation sub-procedure pixel by pixel for each of a plurality of pixels in one row of the N rows of pixels to obtain a plurality of pixel energy consumption values respectively corresponding to the plurality of pixels in said one row of the N rows, and obtaining a row power consumption value corresponding to said one row of the N rows according to the plurality of pixel energy consumption values. The estimation sub-procedure comprises obtaining pixel content information corresponding to one of the plurality of pixels, and determining the pixel energy consumption value according to the pixel content information. The pixel energy consumption value indicates pixel energy consumption generated by performing a predetermined image processing procedure for said one of the plurality of pixels.

3. 发明申请

US20190147135A1 THERMAL ESTIMATION DEVICE AND THERMAL ESTIMATION METHOD 审中-公开
公开(公告)号：US20190147135A1
公开(公告)日：2019-05-16
申请号：US15857156
申请日：2017-12-28
申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
发明人： Yeong-Jar CHANG , Ya-Ting Shyu , Juin-Ming Lu , Yao-Hua Chen , Yen-Fu Chang , Jai-Ming Lin
IPC分类号： G06F17/50
摘要： An embodiment of a thermal estimation device including a temperature model generator, a temperature gradient calculator, and a thermal sensing analyzer is disclosed. The temperature model generator generates a temperature model based on an initial power consumption, an initial area and an initial coordination of a circuit module. The temperature gradient calculator substitutes at least one of a testing area, a testing power or a testing coordinate of the circuit module into the temperature model for correspondingly estimating an temperature estimation function. The thermal sensing analyzer differentiates the temperature estimation function. When an absolute value of a differential result of the temperature estimation function resulted from a constant is closest to zero or is zero, outputting the constant as an optimized parameter.

4. 发明申请

US20180357337A1 TIMING ESIMATION METHOD AND SIMULATOR 审中-公开
公开(公告)号：US20180357337A1
公开(公告)日：2018-12-13
申请号：US15843375
申请日：2017-12-15
申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
发明人： Mei-Ling Chi , Yao-Hua Chen , Hsun-Lun Huang , Juin-Ming Lu
IPC分类号： G06F17/50 , G06F13/16 , G06F13/28
CPC分类号： G06F17/504 , G06F1/28 , G06F13/161 , G06F13/1642 , G06F13/28 , G06F17/5031
摘要： Disclosed are a timing estimation method and a simulator. The method is applied to a function verification model. In the method, the model issues a first access issue at a first time point; receives a first response to the first access issue from the bus at a second time point; calculates a delay time between the first and second time points; determines whether the delay time is longer than or substantially equal to a transmission time corresponding to the first access issue; issues a second access issue if yes; and issues the second access issue in a compensation time counting from the second time point if not. The compensation time is not longer than the difference between the transmission time and the delay time.

5. 发明授权

US11551066B2 Deep neural networks (DNN) hardware accelerator and operation method thereof 有权
公开(公告)号：US11551066B2
公开(公告)日：2023-01-10
申请号：US16248042
申请日：2019-01-15
申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
发明人： Yao-Hua Chen , Chun-Chen Chen , Chih-Tsun Huang , Jing-Jia Liou , Chun-Hung Lai , Juin-Ming Lu
IPC分类号： G06F3/06 , G06N3/063 , G06F13/42 , G06F9/30
摘要： A DNN hardware accelerator and an operation method of the DNN hardware accelerator are provided. The DNN hardware accelerator includes: a network distributor for receiving an input data and distributing respective bandwidth of a plurality of data types of a target data amount based on a plurality of bandwidth ratios of the target data amount; and a processing element array coupled to the network distributor, for communicating data of the data types of the target data amount between the network distributor based on the distributed bandwidth of the data types.

6. 发明授权

US10365829B2 Memory transaction-level modeling method and system 有权
公开(公告)号：US10365829B2
公开(公告)日：2019-07-30
申请号：US15391082
申请日：2016-12-27
申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
发明人： Yao-Hua Chen , Che-Wei Hsu , Juin-Ming Lu , Wei-Shiang Lin , Jing-Jia Liou , Chih-Tsun Huang
IPC分类号： G06F3/00 , G06F3/06 , G06F12/02 , G06F12/06 , G11C7/22
摘要： A memory transaction-level modeling method and a memory transaction-level modeling system are provided. The memory transaction-level modeling method is used for simulating the operation of outputting at least one command to the memory. The memory includes a plurality of banks each of which corresponds with a bank status table. The memory transaction-level modeling method includes the following steps: An event is received. Whether one of the bank status tables is needed to be updated is determined. If one of the bank status tables is needed to be updated, this bank status table is recovered according to a TMP queue. A command is outputted to the memory according to a command queue. The outputted command is stored in the TMP queue. Some of the bank status tables are updated and others of the bank status tables are kept unchanged.

7. 发明申请

US20160148335A1 DATA-PROCESSING APPARATUS AND OPERATION METHOD THEREOF 有权
标题翻译：数据处理装置及其操作方法
公开(公告)号：US20160148335A1
公开(公告)日：2016-05-26
申请号：US14551089
申请日：2014-11-24
申请人： Industrial Technology Research Institute
发明人： Hsu-Yao Huang , I-Hsuan Lu , Tai-Hua Lu , Shau-Yin Tseng , Juin-Ming Lu
IPC分类号： G06T1/20 , G06T7/40
CPC分类号： G06T1/20
摘要： A data-processing apparatus and an operation method thereof are provided. The data-processing apparatus includes a tiling circuit and a post-stage processing circuit. The tiling circuit is configured to receive input data. The tiling circuit divides a current frame of the input data into at least one tile and checks a motion state of the current tile in the at least one tile. The post-stage processing circuit is coupled to the tiling circuit to receive the current tile. The post-stage processing circuit performs post processing on the current tile to generate a processed current tile of the current frame or to obtain a processed corresponding tile of a previous frame and serves it as the processed current tile of the current frame, according to the motion state of the current tile.
摘要翻译：提供了一种数据处理装置及其操作方法。数据处理装置包括平铺电路和后级处理电路。拼接电路被配置为接收输入数据。平铺电路将输入数据的当前帧划分成至少一个瓦片，并检查至少一个瓦片中当前瓦片的运动状态。后级处理电路耦合到平铺电路以接收当前瓦片。后级处理电路对当前片进行后处理以产生当前帧的经处理的当前片，或者获得前一帧的经处理的对应片，并将其作为当前帧的被处理当前片，并根据当前瓦片的运动状态。

8. 发明授权

US11113580B2 Image classification system and method 有权
公开(公告)号：US11113580B2
公开(公告)日：2021-09-07
申请号：US16731001
申请日：2019-12-30
申请人： Industrial Technology Research Institute
发明人： Jiung-Yao Huang , Hsin-Lung Wu , Juin-Ming Lu
IPC分类号： G06K9/00 , G06K9/62 , G06T3/40 , G06T9/00
摘要： An image classification system includes a storage device, a computing device and a first processing device. The storage device stores a plurality of pseudo-centroid datasets, wherein the pseudo-centroid datasets correspond to a plurality of units of first image dataset, and the number of pseudo-centroid data points of each of the pseudo-centroid datasets is much smaller than the number of data points of each of the units of first image dataset. The computing device receives the second image data and computes a plurality of feature values of the second image data. The first processing device receives the feature values and the pseudo-centroid datasets, and compares the feature values with the pseudo-centroid data points to identify and classify the second image data.

9. 发明申请

US20180074702A1 MEMORY TRANSACTION-LEVEL MODELING METHOD AND SYSTEM 审中-公开
公开(公告)号：US20180074702A1
公开(公告)日：2018-03-15
申请号：US15391082
申请日：2016-12-27
申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
发明人： Yao-Hua Chen , Che-Wei Hsu , Juin-Ming Lu , Wei-Shiang Lin , Jing-Jia Liou , Chih-Tsun Huang
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G06F12/0215 , G06F12/0607 , G11C7/22
摘要： A memory transaction-level modeling method and a memory transaction-level modeling system are provided. The memory transaction-level modeling method is used for simulating the operation of outputting at least one command to the memory. The memory includes a plurality of banks each of which corresponds with a bank status table. The memory transaction-level modeling method includes the following steps: An event is received. Whether one of the bank status tables is needed to be updated is determined. If one of the bank status tables is needed to be updated, this bank status table is recovered according to a TMP queue. A command is outputted to the memory according to a command queue. The outputted command is stored in the TMP queue. Some of the bank status tables are updated and others of the bank status tables are kept unchanged.

10. 发明授权

US09773080B2 Thermal simulation device and method 有权
公开(公告)号：US09773080B2
公开(公告)日：2017-09-26
申请号：US14985204
申请日：2015-12-30
申请人： Industrial Technology Research Institute
发明人： Yeong-Jar Chang , Juin-Ming Lu , Liang-Chia Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5027
摘要： A thermal simulation device is applied to a transaction-level designed chip which includes a plurality of intellectual properties. The thermal simulation device includes a plurality of thermal-aware transaction-level power model circuits, a simulator, a translator and a thermal emulator. The thermal-aware transaction-level power model circuits corresponds to the respective intellectual properties, and are configured to a corresponding power information for each of the intellectual properties, and dynamically adjusts the power information according to temperature information. The simulator is configured to generate the corresponding temperature information of the intellectual properties according to compatible information. The translator is configured to generate the compatible information which is compatible with the simulator. The thermal emulator is configured to trigger the simulator and transmit the temperature information to the intellectual properties.

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