专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20210183711A1 SELF-ALIGNED CONTACTS FOR NANOSHEET FIELD EFFECT TRANSISTOR DEVICES 有权
公开(公告)号：US20210183711A1
公开(公告)日：2021-06-17
申请号：US17110604
申请日：2020-12-03
申请人： IMEC vzw
发明人： Eugenio Dentoni Litta , Juergen Boemmels , Julien Ryckaert , Naoto Horiguchi , Pieter Weckx
IPC分类号： H01L21/8238 , H01L27/092 , H01L23/528 , H01L29/06 , H01L29/423 , H01L29/417 , H01L29/786 , H01L21/02 , H01L21/762 , H01L29/66
摘要： In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer. The method can further comprise depositing a contact material over the transistor structures and the first and second spacer, filling the trench and contacting the first source/drain portion of the first transistor structure, and etching back the contact material layer below a top surface of the second spacer.

2. 发明授权

US09633891B2 Method for forming a transistor structure comprising a fin-shaped channel structure 有权
公开(公告)号：US09633891B2
公开(公告)日：2017-04-25
申请号：US14924832
申请日：2015-10-28
申请人： IMEC VZW
发明人： Nadine Collaert , Geert Eneman , Naoto Horiguchi , Min-Soo Kim , Rita Rooyackers , Anabela Veloso , Liesbeth Witters
IPC分类号： H01L21/762 , H01L21/32 , H01L21/3205 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H01L21/76224 , H01L21/32 , H01L21/32055 , H01L29/0649 , H01L29/42392 , H01L29/66742 , H01L29/78696
摘要： An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

3. 发明申请

US20160126131A1 Method for Forming a Transistor Structure Comprising a Fin-Shaped Channel Structure 有权
标题翻译：形成包括鳍形通道结构的晶体管结构的方法
公开(公告)号：US20160126131A1
公开(公告)日：2016-05-05
申请号：US14924832
申请日：2015-10-28
申请人： IMEC VZW
发明人： Nadine Collaert , Geert Eneman , Naoto Horiguchi , Min-Soo Kim , Rita Rooyackers , Anabela Veloso , Liesbeth Witters
IPC分类号： H01L21/762 , H01L21/3205 , H01L29/06 , H01L21/32
CPC分类号： H01L21/76224 , H01L21/32 , H01L21/32055 , H01L29/0649 , H01L29/42392 , H01L29/66742 , H01L29/78696
摘要： An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.
摘要翻译：一个示例性方法包括在由相邻STI结构限定的沟槽中提供层堆叠，并使邻近层堆叠的STI结构凹陷，从而暴露层堆叠的上部，上部至少包括沟道部分。该方法还包括在层堆叠的上部提供一个或多个保护层，然后进一步将STI结构选择性地凹入保护层和层堆叠，从而暴露层堆叠的中心部分。并且该方法包括去除层堆叠的中心部分，导致层叠体的独立上部和下部在物理上彼此分离。

4. 发明授权

US11462443B2 Self-aligned contacts for nanosheet field effect transistor devices 有权
公开(公告)号：US11462443B2
公开(公告)日：2022-10-04
申请号：US17110604
申请日：2020-12-03
申请人： IMEC vzw
发明人： Eugenio Dentoni Litta , Juergen Boemmels , Julien Ryckaert , Naoto Horiguchi , Pieter Weckx
IPC分类号： H01L21/8238 , H01L27/092 , H01L23/528 , H01L29/06 , H01L29/423 , H01L29/417 , H01L29/786 , H01L21/02 , H01L21/762 , H01L29/66
摘要： In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer. The method can further comprise depositing a contact material over the transistor structures and the first and second spacer, filling the trench and contacting the first source/drain portion of the first transistor structure, and etching back the contact material layer below a top surface of the second spacer.

5. 发明申请

US20180330997A1 METHOD OF FORMING VERTICAL TRANSISTOR DEVICE 审中-公开
公开(公告)号：US20180330997A1
公开(公告)日：2018-11-15
申请号：US15977381
申请日：2018-05-11
申请人： IMEC VZW , Vrije Universiteit Brussel
发明人： Julien Ryckaert , Naoto Horiguchi , Dan Mocuta , Trong Huynh Bao
IPC分类号： H01L21/8238 , H01L21/285 , H01L21/306 , H01L21/308 , H01L21/762 , H01L23/528 , H01L27/11 , H01L27/092 , H01L29/06 , H01L29/45 , H01L29/78
摘要： The disclosed technology generally relates to semiconductor fabrication and more particularly to forming vertical transistor devices. In an aspect, a method of forming a vertical transistor device includes forming, on a substrate, a fin comprising a stack including a first layer, a second layer formed above the first layer and a third layer formed above the second layer. The method additionally includes forming a gate layer serving as an etch mask above the third layer. The method further includes etching the second and third layers of the fin using the gate layer as the etch mask to form a pillar. First and third layers of the pillar define a source region and a drain region, respectively, of the vertical transistor device. A second layer of the pillar defines a channel region of the vertical transistor device. The gate layer comprises a gate electrode arranged on at least one sidewall of the second layer.

6. 发明申请

US20150111351A1 Method for Manufacturing a Field Effect Transistor of a Non-Planar Type 有权
标题翻译：非平面型场效应晶体管的制造方法
公开(公告)号：US20150111351A1
公开(公告)日：2015-04-23
申请号：US14521083
申请日：2014-10-22
申请人： IMEC VZW
发明人： Min-Soo Kim , Guillaume Boccardi , Soon Aik Chew , Naoto Horiguchi
IPC分类号： H01L21/8238 , H01L21/762 , H01L21/02 , H01L29/66 , H01L29/06
CPC分类号： H01L21/823821 , H01L21/02126 , H01L21/76205 , H01L21/82385 , H01L21/823878 , H01L29/0653 , H01L29/1054 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/6681 , H01L29/7851
摘要： A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures. Further, the method includes removing an upper portion of at least two shallow trench isolation structures to expose at least a portion of the sidewalls of the fin structures within the gate trench, and forming a final gate stack in the gate trench.
摘要翻译：一种用于制造非平面型场效应晶体管的方法，包括提供具有初始平面的前主表面的基板，并且在所述前表面上的所述基板中提供浅沟槽隔离结构，从而在所述基板中限定多个鳍结构衬底之间的浅沟槽隔离结构。浅沟槽隔离结构和翅片结构的顶表面邻接在共同的平坦表面上，翅片结构的侧壁被浅沟槽隔离结构完全隐藏。该方法还包括在公共平面上的多个翅片结构的中心部分上形成虚拟栅极结构，在虚拟栅极结构周围形成介质间隔物结构，以及去除伪栅极结构，由此留下由电介质间隔结构。此外，该方法包括去除至少两个浅沟槽隔离结构的上部以暴露栅极沟槽内的翅片结构的侧壁的至少一部分，以及在栅极沟槽中形成最终的栅极叠层。

7. 发明授权

US11114435B2 FinFET having locally higher fin-to-fin pitch 有权
公开(公告)号：US11114435B2
公开(公告)日：2021-09-07
申请号：US15382376
申请日：2016-12-16
申请人： IMEC VZW , Katholieke Universiteit Leuven
发明人： Geert Hellings , Roman Boschke , Dimitri Linten , Naoto Horiguchi
IPC分类号： H01L27/088 , H01L29/78 , H01L21/8234 , H01L29/06 , H01L29/417 , H01L29/66
摘要： The disclosed technology generally relates to semiconductor devices, and more particularly to FinFET transistors. In one aspect, at least three fins are arranged to extend in parallel in a first direction and are laterally separated from each other in a second direction by shallow trench isolation structures having a first fin spacing, where at least a portion of each fin protrudes out from a substrate. At least a portion of each of a first fin and a second fin of the at least three fins vertically protrude to a level higher than an upper surface of the shallow trench isolation structures. A third fin is formed laterally between the first fin and the second fin in the second direction, where the third fin has a non-protruding region which extends vertically to a level below or equal to the upper surface of the shallow trench isolation structures.

8. 发明授权

US10361268B2 Internal spacers for nanowire semiconductor devices 有权
公开(公告)号：US10361268B2
公开(公告)日：2019-07-23
申请号：US15907878
申请日：2018-02-28
申请人： IMEC VZW
发明人： Kurt Wostyn , Hans Mertens , Liesbeth Witters , Andriy Hikavyy , Naoto Horiguchi
IPC分类号： H01L29/06 , H01L29/66 , B82Y40/00 , H01L21/8234 , H01L29/08 , B82Y10/00 , H01L29/417 , H01L29/775 , H01L21/311
摘要： A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

9. 发明申请

US20180254321A1 Internal Spacers for Nanowire Semiconductor Devices 审中-公开
公开(公告)号：US20180254321A1
公开(公告)日：2018-09-06
申请号：US15907878
申请日：2018-02-28
申请人： IMEC VZW
发明人： Kurt Wostyn , Hans Mertens , Liesbeth Witters , Andriy Hikavyy , Naoto Horiguchi
IPC分类号： H01L29/06 , H01L29/66 , H01L21/8234 , H01L29/08
CPC分类号： H01L29/0653 , B82Y10/00 , B82Y40/00 , H01L21/31111 , H01L21/31116 , H01L21/823425 , H01L29/0669 , H01L29/0673 , H01L29/0847 , H01L29/41725 , H01L29/66439 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6681 , H01L29/775
摘要： A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

10. 发明申请

US20180174927A1 Contacts in Semiconductor Devices 审中-公开
公开(公告)号：US20180174927A1
公开(公告)日：2018-06-21
申请号：US15819049
申请日：2017-11-21
申请人： IMEC VZW
发明人： Naoto Horiguchi , Andriy Hikavyy , Steven Demuynck
IPC分类号： H01L21/8238 , H01L21/02 , H01L21/306 , H01L29/08 , H01L29/78 , H01L29/786 , H01L29/06 , H01L27/092
CPC分类号： H01L21/823871 , B82Y10/00 , H01L21/02603 , H01L21/30604 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L27/092 , H01L27/0924 , H01L29/045 , H01L29/0673 , H01L29/0847 , H01L29/401 , H01L29/413 , H01L29/417 , H01L29/41791 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/785 , H01L29/7851 , H01L29/78618 , H01L29/78696 , H01L2029/7858
摘要： An example embodiment relates to a method for making a contact to a source or drain region of a semiconductor device. The method may include providing the semiconductor device having at least one source or drain region, the source or drain region having an exposed area. The method may further include partially etching the source or drain region such that the exposed area is increased. The method may further include providing a contact covering at least the etched part of the source or drain region. The contact may contact the source or drain region on at least 3 sides of the source or drain region.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式