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1. 发明授权

US09244701B2 Method for system scenario based design of dynamic embedded systems 有权
标题翻译：基于动态嵌入式系统的系统场景设计方法
公开(公告)号：US09244701B2
公开(公告)日：2016-01-26
申请号：US13940247
申请日：2013-07-11
申请人： IMEC , Stichting IMEC Nederland , Katholieke Universiteit Leuven, K.U. LEUVEN R&D
发明人： Francky Catthoor , Evangelos Bempelis , Wim Van Thillo , Praveen Raghavan , Robert Fasthuber , Elena Hammari , Per Gunnar Kjeldsberg , Jos Huisken
IPC分类号： G06F3/0484 , G06F9/445 , G06F17/50
CPC分类号： G06F9/44505 , G06F17/5045
摘要： Methods are disclosed for system scenario-based design for an embedded platform whereon a dynamic application is implemented. The application meets at least one guaranteed constraint. Temporal correlations are assumed in the behavior of internal data variables used in the application, with the internal data variables representing parameters used for executing a portion of the application. An example method includes determining a distribution over time of an N-dimensional cost function, with N an integer number N≧1, corresponding to the implementation on the platform for a set of combinations of the internal data variables. The method also includes partitioning an N-dimensional cost space in at least two bounded regions, each bounded region containing cost combinations corresponding to combinations of values of the internal data variables of the set that have similar cost and frequency of occurrence, whereby one bounded region is provided for rarely occurring cost combinations.
摘要翻译：对于实现动态应用的嵌入式平台，公开了基于系统场景的设计的方法。应用程序满足至少一个保证约束。在应用程序中使用的内部数据变量的行为假定时间相关性，内部数据变量表示用于执行应用程序的一部分的参数。一个示例性方法包括确定N维成本函数的分布，N为整数N≥1，对应于平台上对于内部数据变量的组合的集合的实现。该方法还包括在至少两个有界区域中分割N维成本空间，每个有界区域包含对应于具有类似成本和发生频率的集合的内部数据变量的值的组合的成本组合，由此一个有界区域是为很少出现的成本组合提供的。

2. 发明申请

US20140019739A1 Method for System Scenario Based Design of Dynamic Embedded Systems 有权
标题翻译：动态嵌入式系统的系统场景设计方法
公开(公告)号：US20140019739A1
公开(公告)日：2014-01-16
申请号：US13940247
申请日：2013-07-11
申请人： IMEC , Katholieke Universiteit Leuven, K.U. LEUVEN R&D , Stichting IMEC Nederland
发明人： Francky Catthoor , Evangelos Bebelis , Wim Van Thillo , Praveen Raghavan , Robert Fasthuber , Elena Hammari , Per Gunnar Kjeldsberg , Jos Huisken
IPC分类号： G06F9/445
CPC分类号： G06F9/44505 , G06F17/5045
摘要： Methods are disclosed for system scenario-based design for an embedded platform whereon a dynamic application is implemented. The application meets at least one guaranteed constraint. Temporal correlations are assumed in the behaviour of internal data variables used in the application, with the internal data variables representing parameters used for executing a portion of the application. An example method includes determining a distribution over time of an N-dimensional cost function, with N an integer number N≧1, corresponding to the implementation on the platform for a set of combinations of the internal data variables. The method also includes partitioning an N-dimensional cost space in at least two bounded regions, each bounded region containing cost combinations corresponding to combinations of values of the internal data variables of the set that have similar cost and frequency of occurrence, whereby one bounded region is provided for rarely occurring cost combinations.
摘要翻译：对于实现动态应用的嵌入式平台，公开了基于系统场景的设计的方法。应用程序满足至少一个保证约束。在应用程序中使用的内部数据变量的行为假定时间相关性，内部数据变量表示用于执行应用程序的一部分的参数。一个示例性方法包括确定N维成本函数的分布，其中N是整数N≥1，对应于平台上对于内部数据变量的组合的集合的实现。该方法还包括在至少两个有界区域中分割N维成本空间，每个有界区域包含对应于具有类似成本和发生频率的集合的内部数据变量的值的组合的成本组合，由此一个有界区域是为很少出现的成本组合提供的。

3. 发明授权

US09632752B2 System and method for implementing a multiplication 有权
公开(公告)号：US09632752B2
公开(公告)日：2017-04-25
申请号：US13721830
申请日：2012-12-20
申请人： IMEC , Katholieke Universiteit Leuven, K.U. LEUVEN R&D , Samsung Electronics Co. Ltd.
发明人： Robert Fasthuber , Praveen Raghavan , Francky Catthoor
IPC分类号： G06F7/523 , G06F7/533 , G06F9/30
CPC分类号： G06F7/523 , G06F7/5332 , G06F9/3001 , G06F9/30025
摘要： The present system and method relate to a system for performing a multiplication. The system is arranged for receiving a first data value, and comprises means for calculating at run time a set of instructions for performing a multiplication using the first data value, storage means for storing the set of instructions calculated at run time, multiplication means arranged for receiving a second data value and at least one instruction from the stored set of instructions and arranged for performing multiplication of the first and the second data values using the at least one instruction.

4. 发明申请

US20130166616A1 System and Method for Implementing a Multiplication 有权
标题翻译：实现乘法的系统和方法
公开(公告)号：US20130166616A1
公开(公告)日：2013-06-27
申请号：US13721830
申请日：2012-12-20
申请人： IMEC , KATHOLIEKE UNIVERSITEIT LEUVEN, K.U. LEUVEN R&D , SAMSUNG ELECTRONICS CO. LTD.
发明人： Robert Fasthuber , Praveen Raghavan , Francky Catthoor
IPC分类号： G06F7/523
CPC分类号： G06F7/523 , G06F7/5332 , G06F9/3001 , G06F9/30025
摘要： The present system and method relate to a system for performing a multiplication. The system is arranged for receiving a first data value, and comprises means for calculating at run time a set of instructions for performing a multiplication using the first data value, storage means for storing the set of instructions calculated at run time, multiplication means arranged for receiving a second data value and at least one instruction from the stored set of instructions and arranged for performing multiplication of the first and the second data values using the at least one instruction.
摘要翻译：本系统和方法涉及用于执行乘法的系统。该系统被设置为用于接收第一数据值，并且包括用于在运行时计算用于使用第一数据值执行乘法的一组指令的装置，用于存储在运行时计算的指令集的存储装置，从所存储的指令集接收第二数据值和至少一个指令，并且被布置为使用所述至少一个指令执行所述第一和第二数据值的相乘。

5. 发明授权

US10073802B2 Inter-cluster data communication network for a dynamic shared communication platform 有权
公开(公告)号：US10073802B2
公开(公告)日：2018-09-11
申请号：US15250067
申请日：2016-08-29
申请人： IMEC VZW , Stichting IMEC Nederland
发明人： Francky Catthoor , Praveen Raghavan
IPC分类号： G06F13/40 , G06F13/42 , G06F15/173 , G06F15/78
CPC分类号： G06F13/4022 , G06F13/4282 , G06F15/17362 , G06F15/7807 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving via N data input ports, N>1, input signals from first clusters of the plurality and for outputting output signals to second clusters of the plurality via M data output ports, M>1. The communication network includes a segmented bus network for interconnecting clusters of the plurality and a controller arranged for concurrently activating up to P parallel data busses of the segmented bus network, thereby forming bidirectional parallel interconnections between P of the N inputs, P

6. 发明申请

US20170083469A1 Inter-Cluster Data Communication Network for a Dynamic Shared Communication Platform 审中-公开
公开(公告)号：US20170083469A1
公开(公告)日：2017-03-23
申请号：US15250067
申请日：2016-08-29
申请人： IMEC VZW , Stichting IMEC Nederland
发明人： Francky Catthoor , Praveen Raghavan
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4022 , G06F13/4282 , G06F15/17362 , G06F15/7807
摘要： The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving via N data input ports, N>1, input signals from first clusters of the plurality and for outputting output signals to second clusters of the plurality via M data output ports, M>1. The communication network includes a segmented bus network for interconnecting clusters of the plurality and a controller arranged for concurrently activating up to P parallel data busses of the segmented bus network, thereby forming bidirectional parallel interconnections between P of the N inputs, P

7. 发明授权

US10355128B2 Double-gate vertical transistor semiconductor device 有权
公开(公告)号：US10355128B2
公开(公告)日：2019-07-16
申请号：US15835703
申请日：2017-12-08
申请人： IMEC VZW , Katholieke Universiteit Leuven, KU LEUVEN R&D
发明人： Praveen Raghavan , Odysseas Zografos
IPC分类号： H01L29/78 , H01L29/66 , H01L21/8234
摘要： A semiconductor device is disclosed that includes a substrate and at least a first, second, third, and fourth vertical transistor supported by the substrate. Each transistor comprises a vertical channel, a polarity gate electrode forming a polarity gate adapted to act on a first portion of the channel to affect a polarity of the channel, and a control gate electrode forming a control gate adapted to act on a second portion of the channel to control the electrical conductivity of the channel. The polarity gate electrode and the control gate electrode of each one of the transistors extend laterally from their respective gate and in mutually opposite directions, and the transistors are laterally spaced from each other and arranged such that the control gate electrodes of the first and third transistor face each other and the control gate electrodes of the second and fourth transistor face each other.

8. 发明申请

US20190034111A1 CONTROL PLANE ORGANIZATION FOR FLEXIBLE DIGITAL DATA PLANE 审中-公开
公开(公告)号：US20190034111A1
公开(公告)日：2019-01-31
申请号：US16028328
申请日：2018-07-05
申请人： IMEC vzw , Katholieke Universiteit Leuven
发明人： Francky Catthoor , Praveen Raghavan , Daniele Garbin , Dimitrios Rodopoulos , Odysseas Zografos
IPC分类号： G06F3/06 , G06N3/08
CPC分类号： G06F3/0646 , G06F3/0604 , G06F3/0673 , G06N3/0445 , G06N3/0454 , G06N3/063 , G06N3/08 , G06N3/088 , G11C7/1006 , G11C11/54 , G11C13/0002 , G11C13/0061 , G11C16/04 , G11C17/165 , G11C2213/71
摘要： A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.

9. 发明授权

US10019361B2 Low-layer memory for a computing platform 有权
公开(公告)号：US10019361B2
公开(公告)日：2018-07-10
申请号：US15250188
申请日：2016-08-29
申请人： IMEC VZW
发明人： Francky Catthoor , Praveen Raghavan , Matthias Hartmann , Komalan Manu Perumkunnil , Jose Ignacio Gomez , Christian Tenllado
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/0811 , G06F3/06 , G06F12/0893 , G06F12/0897 , G11C7/10 , G11C11/16 , G06F15/78 , G06F13/16
CPC分类号： G06F12/0811 , G06F3/0611 , G06F3/0656 , G06F3/0685 , G06F3/0688 , G06F8/41 , G06F8/452 , G06F12/0862 , G06F12/0893 , G06F12/0897 , G06F13/1657 , G06F13/1673 , G06F15/781 , G06F15/7846 , G06F2212/1016 , G06F2212/222 , G06F2212/454 , G06F2212/601 , G06F2212/6028 , G11C7/10 , G11C11/165 , G11C11/1673 , G11C11/1675
摘要： The present disclosure relates to low-layer memory for a computing platform. An example embodiment includes a memory hierarchy being directly connectable to a processor. The memory hierarchy includes at least a level 1, referred to as L1, memory structure comprising a non-volatile memory unit as L1 data memory and a buffer structure (L1-VWB). The buffer structure includes a plurality of interconnected wide registers with an asymmetric organization, wider towards the non-volatile memory unit than towards a data path connectable to the processor. The buffer structure and the non-volatile memory unit are arranged for being directly connectable to a processor so that data words can be read directly from either of the L1 data memory and the buffer structure (L1-VWB) by the processor.

10. 发明授权

US08839082B2 Methods for viterbi decoder implementation 有权
标题翻译：维特比解码器实现方法
公开(公告)号：US08839082B2
公开(公告)日：2014-09-16
申请号：US13739852
申请日：2013-01-11
申请人： IMEC , Samsung Electronics Co. Ltd.
发明人： Francky Catthoor , Frederik Naessens , Praveen Raghavan
IPC分类号： H03M13/03 , G06F11/00 , G06F17/50 , G06F11/22 , H03M13/25 , H03M13/41 , H03M13/00
CPC分类号： H03M13/256 , G06F17/5059 , H03M13/41 , H03M13/65
摘要： Disclosed is a method for selecting a design option for a Viterbi decoder model. In some embodiments, the method includes deriving a set of design options for a Viterbi decoder model by differentiating at least one design parameter, where the at least one design parameter comprises at least a first value for a look-ahead parameter. The method further includes performing an evaluation of each design option in the set of design options in a multi-dimensional design space and, based on the evaluation of each design option, selecting a design option in the set of design options that (i) satisfies a predetermined energy efficiency constraint and (ii) yields at least a second value for the look-ahead parameter, wherein the second value is greater than the first value and satisfies a predetermined area budget.
摘要翻译：公开了一种用于选择维特比解码器模型的设计选项的方法。在一些实施例中，该方法包括通过区分至少一个设计参数来导出维特比解码器模型的一组设计选项，其中至少一个设计参数至少包括用于先行参数的第一值。该方法还包括在多维设计空间中对该组设计选项中的每个设计选项执行评估，并且基于对每个设计选项的评估，在所述一组设计选项中选择（i）满足的设计选项预定的能量效率约束和（ii）产生用于所述先行参数的至少第二值，其中所述第二值大于所述第一值并满足预定区域预算。

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