专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08623739B2 Method of manufacturing semiconductor device using acid diffusion 有权
标题翻译：使用酸扩散制造半导体器件的方法
公开(公告)号：US08623739B2
公开(公告)日：2014-01-07
申请号：US13185897
申请日：2011-07-19
申请人： Hyung-rae Lee , Yool Kang , Kyung-hwan Yoon , Hyoung-hee Kim , So-ra Han , Tae-hoi Park
发明人： Hyung-rae Lee , Yool Kang , Kyung-hwan Yoon , Hyoung-hee Kim , So-ra Han , Tae-hoi Park
IPC分类号： H01L21/76
CPC分类号： H01L27/10891 , G03F7/40 , H01L21/0206 , H01L21/823842 , H01L27/0207 , H01L27/10876 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66606
摘要： A method of manufacturing a semiconductor device includes forming a resist pattern on a first region on a substrate, bringing a descum solution including an acid source into contact with the resist pattern and with a second region of the substrate, decomposing resist residues remaining on the second region of the substrate by using acid obtained from the acid source in the descum solution and removing the decomposed resist residues and the descum solution from the substrate.
摘要翻译：一种制造半导体器件的方法包括在衬底上的第一区域上形成抗蚀剂图案，使包含酸源的除去溶液与抗蚀剂图案接触，并与衬底的第二区域分离，残留在第二区域上的抗蚀剂残留物通过使用从除去溶液中的酸源获得的酸，并从底物除去分解的抗蚀剂残留物和除去溶液的底物区域。

2. 发明申请

US20150364334A1 METHOD OF FORMING PATTERNS AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE 有权
标题翻译：形成图案的方法和制造集成电路装置的方法
公开(公告)号：US20150364334A1
公开(公告)日：2015-12-17
申请号：US14695047
申请日：2015-04-24
申请人： Yool Kang , Dong-won Kim , Ju-young Kim , Tae-hoon Kim , Hye-ji Lee , Su-min Park , Hyung-rae Lee
发明人： Yool Kang , Dong-won Kim , Ju-young Kim , Tae-hoon Kim , Hye-ji Lee , Su-min Park , Hyung-rae Lee
IPC分类号： H01L21/308 , H01L21/311 , H01L21/02 , H01L21/027
CPC分类号： H01L21/3086 , H01L21/0273 , H01L21/0332 , H01L21/0337 , H01L21/3081 , H01L21/31144 , H01L21/32139 , H01L21/76816 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： Provided are a method of forming patterns and a method of manufacturing an integrated circuit device. In the method of forming patterns, a photoresist pattern having a first opening exposing a first region of a target layer is formed. A capping layer is formed at sidewalls of the photoresist pattern defining the first opening. An insoluble region is formed around the first opening by diffusing acid from the capping layer to the inside of the photoresist pattern. A second opening exposing a second region of the target layer is formed by removing a soluble region spaced apart from the first opening, with the insoluble region being interposed therebetween. The target layer is etched using the insoluble region as an etch mask.
摘要翻译：提供形成图案的方法和制造集成电路器件的方法。在形成图案的方法中，形成具有暴露目标层的第一区域的第一开口的光致抗蚀剂图案。在限定第一开口的光致抗蚀剂图案的侧壁处形成覆盖层。通过将酸从封盖层扩散到光致抗蚀剂图案的内部，在第一开口周围形成不溶性区域。通过去除与第一开口间隔开的可溶性区域形成暴露目标层的第二区域的第二开口，其中插入不溶性区域。使用不溶性区域作为蚀刻掩模蚀刻靶层。

3. 发明授权

US08198194B2 Methods of forming p-channel field effect transistors having SiGe source/drain regions 有权
标题翻译：形成具有SiGe源极/漏极区域的p沟道场效应晶体管的方法
公开(公告)号：US08198194B2
公开(公告)日：2012-06-12
申请号：US12729486
申请日：2010-03-23
申请人： Jong Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
发明人： Jong Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
IPC分类号： H01L21/311
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.
摘要翻译：形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。然后在栅电极上图案化掩模层。选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

4. 发明申请

US20110237039A1 Methods of Forming P-Channel Field Effect Transistors Having SiGe Source/Drain Regions 有权
标题翻译：形成具有SiGe源极/漏极区域的P沟道场效应晶体管的方法
公开(公告)号：US20110237039A1
公开(公告)日：2011-09-29
申请号：US12729486
申请日：2010-03-23
申请人： Jong-Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
发明人： Jong-Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer is then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.
摘要翻译：形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。然后在栅极电极上形成掩模层。选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式