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1. 发明申请

US20050142867A1 Method for forming polysilicon plug of semiconductor device 有权
标题翻译：用于形成半导体器件的多晶硅插塞的方法
公开(公告)号：US20050142867A1
公开(公告)日：2005-06-30
申请号：US10879220
申请日：2004-06-30
申请人： Hyung Park , Min Lee , Sang Lee , Hyun Sohn
发明人： Hyung Park , Min Lee , Sang Lee , Hyun Sohn
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L21/60 , H01L21/768
CPC分类号： H01L21/76897 , H01L21/7684
摘要： Disclosed is a method for forming a polysilicon plug of a semiconductor device. The method comprises the steps of: forming a stacked pattern of a wordline and a hard mask film on a semiconductor substrate comprising a cell region and a peripheral circuit region; forming a spacer on a sidewall of the stacked pattern; forming an interlayer insulating film on the semiconductor substrate; polishing the interlayer insulating film via a CMP process using the hard mask film as a polishing barrier film; forming a barrier film on the semiconductor substrate including the interlayer insulating film; selectively etching the barrier film and the interlayer insulating film to form a landing plug contact hole; depositing a polysilicon film filling the landing plug contact hole on the semiconductor substrate; blanket-etching the polysilicon film using the barrier film as an etching barrier film; and polishing the polysilicon film and the barrier film using the hard mask film as a polishing barrier film to form a polysilicon plug.
摘要翻译：公开了一种用于形成半导体器件的多晶硅插塞的方法。该方法包括以下步骤：在包括单元区域和外围电路区域的半导体衬底上形成字线和硬掩模膜的堆叠图案; 在所述堆叠图案的侧壁上形成间隔物; 在半导体衬底上形成层间绝缘膜; 通过使用硬掩模膜作为抛光阻挡膜的CMP工艺来研磨层间绝缘膜; 在包括层间绝缘膜的半导体衬底上形成阻挡膜; 选择性地蚀刻阻挡膜和层间绝缘膜以形成着陆塞接触孔; 在所述半导体衬底上沉积填充所述着地插头接触孔的多晶硅膜; 使用阻挡膜作为蚀刻阻挡膜对多晶硅膜进行绝缘蚀刻; 并使用硬掩模膜作为抛光阻挡膜研磨多晶硅膜和阻挡膜以形成多晶硅插塞。

2. 发明申请

US20060145217A1 CMOS image sensor and method for manufacturing the same 失效
公开(公告)号：US20060145217A1
公开(公告)日：2006-07-06
申请号：US11319487
申请日：2005-12-29
申请人： Hyun Sohn
发明人： Hyun Sohn
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14643 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14645 , H01L27/14689
摘要： A CMOS image sensor and a method for manufacturing the same improves photosensitivity and prevent loss of light by forming a photo-sensing unit under a color filter. The CMOS image sensor may include a plurality of transistors formed on a semiconductor substrate, a metal line formed over the plurality of transistors for electrically connecting the plurality of transistors, and a plurality of photodiodes electrically connected with the plurality of transistors and formed over the metal line.

3. 发明申请

US20060244055A1 Transistor structure of memory device and method for fabricating the same 有权
公开(公告)号：US20060244055A1
公开(公告)日：2006-11-02
申请号：US11201951
申请日：2005-08-10
申请人： Se Jang , Yong Kim , Jae Oh , Jae Roh , Hyun Sohn
发明人： Se Jang , Yong Kim , Jae Oh , Jae Roh , Hyun Sohn
IPC分类号： H01L29/94
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L29/66621 , H01L29/66795 , H01L29/7851
摘要： A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.

4. 发明申请

US20060270177A1 Method for forming capacitor of semiconductor device 失效
公开(公告)号：US20060270177A1
公开(公告)日：2006-11-30
申请号：US11173089
申请日：2005-07-01
申请人： Ki Park , Jae Roh , Hyun Sohn
发明人： Ki Park , Jae Roh , Hyun Sohn
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/65
摘要： Disclosed is a method for forming a capacitor of a semiconductor device. In such a method, a mold insulating layer is formed on an insulating interlayer provided with a storage node plug, and the mold insulating layer is etched to form a hole through which the storage node plug is exposed. Next, a metal storage electrode with an interposed WN layer is formed on a hole surface including the exposed storage node plug and the mold insulating layer is removed. Finally, a dielectric layer and a plate electrode are formed in order on the metal storage electrode.

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