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1. 发明公开

US20230187403A1 METHOD FOR MANUFACTURING DOUBLE-SIDED COOLING TYPE POWER MODULE AND DOUBLE-SIDED COOLING TYPE POWER MODULE 审中-公开
公开(公告)号：US20230187403A1
公开(公告)日：2023-06-15
申请号：US17703057
申请日：2022-03-24
申请人： HYUNDAI MOTOR COMPANY , KIA CORPORATION
发明人： Kyoung-Kook Hong , Su-Bin Kang , Young-Seok Kim
IPC分类号： H01L23/00 , H01L23/373
CPC分类号： H01L24/27 , H01L23/3735 , H01L24/32 , H01L24/33 , H01L24/83 , H01L2224/2711 , H01L2224/3303 , H01L2224/8384 , H01L2224/27438 , H01L2224/29139 , H01L2224/32225 , H01L2224/33181 , H01L2224/83191 , H01L2224/83192 , H01L2224/83201 , H01L2224/83447 , H01L2924/10272
摘要： The present disclosure provides a method for manufacturing a double-sided cooling type power module including separately patterning a bonding material on a base film into two regions, positioning a semiconductor chip on the patterned bonding material, transferring the patterned bonding material to one surface of the semiconductor chip by pressurizing the semiconductor chip, positioning the bonding material of the semiconductor chip on an upper electrode layer formed on an upper substrate to be in contact with the upper electrode layer, and sintering an upper bonding layer by pressurizing and heating the semiconductor chip. According to the present disclosure, it is possible to separately dispose the bonding material on each of gate and source electrode parts on an upper portion of the chip even without protrusion to directly bond the chip and the substrate.

2. 发明申请

US20150183063A1 METHOD OF JOINING SILVER PASTE 审中-公开
标题翻译：加入银浆的方法
公开(公告)号：US20150183063A1
公开(公告)日：2015-07-02
申请号：US14469031
申请日：2014-08-26
申请人： Hyundai Motor Company
发明人： Kyoung-Kook Hong , Youngkyun Jung , Jong Seok Lee , Dae Hwan Chun , Su Bin Kang
IPC分类号： B23K35/30 , B23K35/02 , B22F3/00
CPC分类号： B23K35/3006 , B22F1/0085 , B22F1/0096 , B22F3/00 , B22F2998/10 , B23K35/025 , C22C1/0466 , B22F1/0003 , B22F1/025
摘要： A method of joining silver paste is provided. The method includes preparing silver paste comprising silver powders and lead powders and heating silver paste. The silver powders are then joined.
摘要翻译：提供了一种接合银膏的方法。该方法包括制备包含银粉和铅粉的银膏并加热银浆。然后将银粉末接合。

3. 发明授权

US09029872B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09029872B2
公开(公告)日：2015-05-12
申请号：US14098409
申请日：2013-12-05
申请人： Hyundai Motor Company
发明人： Jong Seok Lee , Kyoung-Kook Hong , Dae Hwan Chun , Youngkyun Jung
IPC分类号： H01L21/00 , H01L29/16 , H01L29/66 , H01L29/78 , H01L29/06 , H01L21/04 , H01L29/417
CPC分类号： H01L29/1608 , H01L21/0455 , H01L29/0623 , H01L29/41766 , H01L29/66068 , H01L29/7813
摘要： The present inventive concept has been made in an effort to improve the breakdown voltage of a silicon carbide MOSFET using a trench gate.A semiconductor device according to the present inventive concept includes a p type pillar region disposed below the trench, spaced apart from the trench or a first p type pillar region and a second p type pillar region disposed below the trench and corresponding to two corners of the trench.
摘要翻译：本发明构思是为了改善使用沟槽栅极的碳化硅MOSFET的击穿电压。根据本发明构思的半导体器件包括设置在沟槽下方的与沟槽间隔开的p型柱状区域或设置在沟槽下方并对应于沟槽的两个角的第一p型柱状区域和第二p型支柱区域。

4. 发明授权

US09006746B2 Schottky barrier diode and method for manufacturing schottky barrier diode 有权
标题翻译：肖特基势垒二极管及制造肖特基势垒二极管的方法
公开(公告)号：US09006746B2
公开(公告)日：2015-04-14
申请号：US14143649
申请日：2013-12-30
申请人： Hyundai Motor Company
发明人： Youngkyun Jung , Dae Hwan Chun , Kyoung-Kook Hong , Jong Seok Lee , Junghee Park
IPC分类号： H01L29/161 , H01L29/872 , H01L29/66 , H01L29/16
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/1608 , H01L29/6606
摘要： A Schottky barrier diode and a method of manufacturing the diode are provided. The diode includes an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate and a plurality of p+ regions disposed within the n− type epitaxial layer. An n+ type epitaxial layer is disposed on the n− type epitaxial layer, a Schottky electrode is disposed on the n+ type epitaxial layer, and an ohmic electrode is disposed on a second surface of the n+ type silicon carbide substrate. The n+ type epitaxial layer includes a plurality of pillar parts disposed on the n− type epitaxial layer and a plurality of openings disposed between the pillar parts and that expose the p+ regions. Each of the pillar parts includes substantially straight parts that contact the n− type epitaxial layer and substantially curved parts that extend from the substantially straight parts.
摘要翻译：提供肖特基势垒二极管和制造二极管的方法。二极管包括设置在n +型碳化硅衬底的第一表面上的n型外延层和设置在n型外延层内的多个p +区。在n型外延层上设置n +型外延层，在n +型外延层上设置肖特基电极，在n +型碳化硅基板的第二面上设置欧姆电极。 n +型外延层包括设置在n型外延层上的多个柱部分和设置在柱部分之间并暴露p +区域的多个开口。每个支柱部分包括接触n型外延层的基本上直的部分和从基本上直的部分延伸的基本上弯曲的部分。

5. 发明授权

US09236500B2 Schottky barrier diode and method for manufacturing schottky barrier diode 有权
标题翻译：肖特基势垒二极管及制造肖特基势垒二极管的方法
公开(公告)号：US09236500B2
公开(公告)日：2016-01-12
申请号：US14143735
申请日：2013-12-30
申请人： Hyundai Motor Company
发明人： Jong Seok Lee , Kyoung-Kook Hong , Dae Hwan Chun , Youngkyun Jung
IPC分类号： H01L29/06 , H01L29/872 , H01L29/66 , H01L29/16
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0661 , H01L29/1608 , H01L29/6606 , H01L29/66143
摘要： A Schottky barrier diode and a method of manufacturing the Schottky barrier diode are provided. The diode includes an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate and having an upper surface, a lower surface, and an inclined surface that connects the upper surface and the lower surface. A p region is disposed on the inclined surface of the n− type epitaxial layer and a Schottky electrode is disposed on the upper surface of the n− type epitaxial layer and the p region. In addition, an ohmic electrode is disposed on a second surface of the n+ type silicon carbide substrate.
摘要翻译：提供肖特基势垒二极管和制造肖特基势垒二极管的方法。二极管包括n型外延层，其设置在n +型碳化硅衬底的第一表面上，并具有上表面，下表面和连接上表面和下表面的倾斜表面。 p区设置在n型外延层的倾斜面上，肖特基电极设置在n型外延层和p区的上表面上。此外，欧姆电极设置在n +型碳化硅衬底的第二表面上。

6. 发明授权

US09159847B2 Schottky barrier diode and method of manufacturing the same 有权
标题翻译：肖特基势垒二极管及其制造方法
公开(公告)号：US09159847B2
公开(公告)日：2015-10-13
申请号：US14098359
申请日：2013-12-05
申请人： Hyundai Motor Company
发明人： Jong Seok Lee , Kyoung-Kook Hong , Dae Hwan Chun , Youngkyun Jung
IPC分类号： H01L31/0312 , H01L29/872 , H01L29/16 , H01L29/66 , H01L29/06 , H01L29/08
CPC分类号： H01L29/872 , H01L29/0615 , H01L29/0619 , H01L29/0804 , H01L29/1608 , H01L29/6606
摘要： A schottky barrier diode includes: an n− type epitaxial layer that is disposed at a first surface of an n+ type silicon carbide substrate; a plurality of n type pillar areas that are disposed at the inside of the n− type epitaxial layer and that are disposed at a first portion of the first surface of the n+ type silicon carbide substrate; a p type area that is disposed at the inside of the n− type epitaxial layer and that is extended in a direction perpendicular to the n type pillar areas; a plurality of p+ areas in which the n− type epitaxial layer is disposed at a surface thereof and that are separated from the n type pillar areas and the p type area; a schottky electrode that is disposed on the n− type epitaxial layer and the p+ areas; and an ohmic electrode that is disposed at a second surface of the n+ type silicon carbide substrate.
摘要翻译：肖特基势垒二极管包括：n型外延层，其设置在n +型碳化硅衬底的第一表面; 多个n型支柱区域，其设置在n型外延层的内部，并且设置在n +型碳化硅衬底的第一表面的第一部分; p型区域，其设置在所述n型外延层的内部，并且在垂直于所述n型支柱区域的方向上延伸; 多个p +区域，其中n型外延层设置在其表面并且与n型支柱区域和p型区域分离; 设置在n型外延层和p +区域上的肖特基电极; 以及设置在n +型碳化硅衬底的第二表面的欧姆电极。

7. 发明授权

US09142644B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09142644B2
公开(公告)日：2015-09-22
申请号：US14079222
申请日：2013-11-13
申请人： Hyundai Motor Company
发明人： Jong Seok Lee , Kyoung-Kook Hong , Dae Hwan Chun , Youngkyun Jung
IPC分类号： H01L29/772 , H01L29/66 , H01L29/06 , H01L29/78 , H01L29/423
CPC分类号： H01L29/66666 , H01L29/0688 , H01L29/1608 , H01L29/41766 , H01L29/42312 , H01L29/42316 , H01L29/4232 , H01L29/4236 , H01L29/66068 , H01L29/66734 , H01L29/66787 , H01L29/66795 , H01L29/7802 , H01L29/7813 , H01L29/7834
摘要： The present inventive concept has been made in an effort to increase the width of a channel in a silicon carbide MOSFET using a trench gate.According to the exemplary embodiment of the present inventive concept, the width of a channel can be increased, compared with the conventional art, by forming a plurality of protrusions extending to the p type epitaxial layer on both sides of the trench.
摘要翻译：本发明构思是为了增加使用沟槽栅极的碳化硅MOSFET中的沟道的宽度。根据本发明构思的示例性实施例，与传统技术相比，可以通过在沟槽的两侧形成延伸到p型外延层的多个突起来增加通道的宽度。

8. 发明申请

US20140187004A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20140187004A1
公开(公告)日：2014-07-03
申请号：US13830260
申请日：2013-03-14
申请人： HYUNDAI MOTOR COMPANY
发明人： Dae Hwan Chun , Jong Seok Lee , Kyoung-Kook Hong , Youngkyun Jung
IPC分类号： H01L29/66
CPC分类号： H01L29/0634 , H01L29/1608 , H01L29/2003 , H01L29/41766 , H01L29/66068 , H01L29/66727 , H01L29/66734 , H01L29/7802 , H01L29/7813
摘要： Disclosed is a method for fabricating a semiconductor device including: sequentially forming a first insulating film and a first barrier layer on a first surface of a substrate; etching the first barrier layer to form a first barrier layer pattern; etching the first insulating film to form a first insulating film pattern; removing the first barrier layer pattern and forming a first type epitaxial layer on an exposed first portion of the substrate; forming a second insulating film and a second barrier layer on the first type epitaxial layer and the first insulating film pattern; etching the second barrier layer to form a second barrier layer pattern; etching the second insulating film to form a second insulating film pattern, and etching the first insulating film pattern; and forming a second type epitaxial layer on an exposed second portion of the first surface of the n substrate.
摘要翻译：公开了一种制造半导体器件的方法，包括：在衬底的第一表面上依次形成第一绝缘膜和第一阻挡层; 蚀刻第一阻挡层以形成第一阻挡层图案; 蚀刻第一绝缘膜以形成第一绝缘膜图案; 去除所述第一阻挡层图案并在所述基板的暴露的第一部分上形成第一类型的外延层; 在所述第一型外延层和所述第一绝缘膜图案上形成第二绝缘膜和第二阻挡层; 蚀刻第二阻挡层以形成第二阻挡层图案; 蚀刻第二绝缘膜以形成第二绝缘膜图案，并蚀刻第一绝缘膜图案; 以及在所述n基板的所述第一表面的暴露的第二部分上形成第二类型的外延层。

9. 发明申请

US20140117379A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140117379A1
公开(公告)日：2014-05-01
申请号：US13729641
申请日：2012-12-28
申请人： HYUNDAI MOTOR COMPANY
发明人： Youngkyun JUNG , Kyoung-Kook Hong , Jong Seok Lee , Dae Hwan Chun
IPC分类号： H01L29/16 , H01L21/36
CPC分类号： H01L29/1608 , H01L21/0475 , H01L21/049 , H01L29/42356 , H01L29/7827
摘要： A method of manufacturing a semiconductor device includes sequentially forming an n− type epitaxial layer, a p type epitaxial layer, and a first n+ region on a first surface of an n+ type silicon carbide substrate, and forming a trench through the first n+ region and the p type epitaxial layer, wherein the forming of the trench includes forming a photosensitive layer pattern on the first n+ region, etching the first n+ region and the p type epitaxial layer by using the photosensitive layer pattern as a mask, forming a buffer layer by using amorphous carbon on the first n+ region after the photosensitive layer pattern is removed, forming a buffer layer pattern by etching the buffer layer, etching using the buffer layer pattern as the mask, isotropically etching to form a second portion of the trench, and removing the buffer layer pattern.
摘要翻译：一种制造半导体器件的方法包括：在n +型碳化硅衬底的第一表面上依次形成n-型外延层，ap型外延层和第一n +区，以及通过第一n +区形成沟槽， p型外延层，其中所述沟槽的形成包括在所述第一n +区上形成感光层图案，通过使用所述感光层图案作为掩模蚀刻所述第一n +区和所述p型外延层，通过使用除去感光层图案后的第一n +区域上的无定形碳，通过蚀刻缓冲层形成缓冲层图案，使用缓冲层图案进行蚀刻作为掩模，各向同性蚀刻以形成沟槽的第二部分，缓冲层图案。

10. 发明申请

US20140097447A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140097447A1
公开(公告)日：2014-04-10
申请号：US13709905
申请日：2012-12-10
申请人： HYUNDAI MOTOR COMPANY
发明人： Jong Seok Lee , Kyoung-Kook Hong
IPC分类号： H01L29/16 , H01L29/66 , H01L29/78
CPC分类号： H01L29/1608 , H01L29/0619 , H01L29/0657 , H01L29/0847 , H01L29/66068 , H01L29/7827 , H01L29/7828
摘要： Disclosed herein is a semiconductor device and method of manufacturing the semiconductor, including an n type buffer layer disposed on a first surface of an n+ type silicon carbide substrate, an n− type epitaxial layer disposed on the n type buffer layer, a first type of trench disposed on each side of a second type of trench, wherein the trenches are disposed in the n− type epitaxial layer, an n+ region disposed on the n− type epitaxial layer, a p+ region disposed in each first type of trench, a gate insulating layer disposed in the second trench, a gate material disposed on the gate insulating layer, an oxidation layer disposed on the gate material, a source electrode disposed on the n+ region, oxidation layer, and p+ region, and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate.
摘要翻译：本发明公开了半导体器件及其制造方法，该半导体器件及其制造方法包括n型缓冲层，其设置在n +型碳化硅衬底的第一表面上，n型外延层设置在n型缓冲层上，第一种类型沟槽，其布置在第二类型沟槽的每一侧上，其中沟槽设置在n型外延层中，n +区域设置在n型外延层上，p +区域设置在每个第一类型的沟槽中，栅极设置在第二沟槽中的绝缘层，设置在栅极绝缘层上的栅极材料，设置在栅极材料上的氧化层，设置在n +区域上的源电极，氧化层和p +区域，以及设置在栅极材料上的漏电极 n +型碳化硅衬底的第二表面。

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