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1. 发明授权

US07710807B2 Sense amplifiers having MOS transistors therein with different threshold voltages and/or that support different threshold voltage biasing 有权
标题翻译：具有其中具有不同阈值电压的MOS晶体管和/或支持不同阈值电压偏置的感测放大器
公开(公告)号：US07710807B2
公开(公告)日：2010-05-04
申请号：US12021762
申请日：2008-01-29
申请人： Hyun-Seok Lee , Jong-Hyun Choi , Ki-Chul Chun , Jong-Eon Lee
发明人： Hyun-Seok Lee , Jong-Hyun Choi , Ki-Chul Chun , Jong-Eon Lee
IPC分类号： G11C7/02
CPC分类号： G11C7/065 , G11C11/406 , G11C11/4091 , G11C2211/4065
摘要： A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. This electrically coupling is provided so that each of the first pair of MOS transistors has a first source/drain terminal electrically connected to a corresponding one of the pair of sense bit lines and the second source/drain terminals of the first pair of MOS transistors are electrically connected together. The first pair of MOS transistors of first conductivity type is configured to have different threshold voltages or support different threshold voltage biasing. The second MOS sense amplifier has a first pair of MOS transistors of second conductivity type therein, which are electrically coupled across the pair of sense bit lines.
摘要翻译：感测放大器包括一对感测位线和第一和第二MOS读出放大器。第一MOS读出放大器在其中具有第一导电类型的第一对MOS晶体管，其电耦合在该对感测位线之间。该电耦合被提供为使得第一对MOS晶体管中的每一个具有电连接到该对感测位线中的相应一个和第一对MOS晶体管的第二源极/漏极端子的第一源极/漏极端子电连接在一起。第一导电类型的第一对MOS晶体管被配置为具有不同的阈值电压或支持不同的阈值电压偏置。第二MOS读出放大器具有第一对第二导电类型的MOS晶体管，它们在一对感测位线之间电耦合。

2. 发明授权

US07345939B2 Sense amplifiers having MOS transistors therein with different threshold voltages and/or that support different threshold voltage biasing 有权
标题翻译：具有其中具有不同阈值电压的MOS晶体管和/或支持不同阈值电压偏置的感测放大器
公开(公告)号：US07345939B2
公开(公告)日：2008-03-18
申请号：US11185351
申请日：2005-07-20
申请人： Hyun-Seok Lee , Jong-Hyun Choi , Ki-Chul Chun , Jong-Eon Lee
发明人： Hyun-Seok Lee , Jong-Hyun Choi , Ki-Chul Chun , Jong-Eon Lee
IPC分类号： G11C7/02
CPC分类号： G11C7/065 , G11C11/406 , G11C11/4091 , G11C2211/4065
摘要： A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. This electrically coupling is provided so that each of the first pair of MOS transistors has a first source/drain terminal electrically connected to a corresponding one of the pair of sense bit lines and the second source/drain terminals of the first pair of MOS transistors are electrically connected together. The first pair of MOS transistors of first conductivity type are configured to have different threshold voltages or support different threshold voltage biasing. The second MOS sense amplifier has a first pair of MOS transistors of second conductivity type therein, which are electrically coupled across the pair of sense bit lines.
摘要翻译：感测放大器包括一对感测位线和第一和第二MOS读出放大器。第一MOS读出放大器在其中具有第一导电类型的第一对MOS晶体管，其电耦合在该对感测位线之间。该电耦合被提供为使得第一对MOS晶体管中的每一个具有电连接到该对感测位线中的相应一个和第一对MOS晶体管的第二源极/漏极端子的第一源极/漏极端子电连接在一起。第一导电类型的第一对MOS晶体管被配置为具有不同的阈值电压或支持不同的阈值电压偏置。第二MOS读出放大器具有第一对第二导电类型的MOS晶体管，它们在一对感测位线之间电耦合。

3. 发明申请

US20060023537A1 Semiconductor memory devices and method of sensing bit line thereof 有权
标题翻译：半导体存储器件及其位线检测方法
公开(公告)号：US20060023537A1
公开(公告)日：2006-02-02
申请号：US11185351
申请日：2005-07-20
申请人： Hyun-Seok Lee , Jong-Hyun Choi , Ki-Chul Chun , Jong-Eon Lee
发明人： Hyun-Seok Lee , Jong-Hyun Choi , Ki-Chul Chun , Jong-Eon Lee
IPC分类号： G11C7/02
CPC分类号： G11C7/065 , G11C11/406 , G11C11/4091 , G11C2211/4065
摘要： A semiconductor memory device and a bit line sensing method thereof are disclosed. The semiconductor memory device includes a first memory cell connected between a first word line accessed by a first address and an inverted bit line; a second memory cell connected between a second word line accessed by a second address and a bit line; a first type sense amplifier serially connected between the bit line and the inverted bit line and having a first type first MOS transistor sensing the inverted bit line and a first type second MOS transistor sensing the bit line if a first enable signal of a first voltage is applied; a second type first sense amplifier serially connected between the bit line and the inverted bit line and having a second type first MOS transistor sensing the inverted bit line and a second type second MOS transistor sensing the bit line if a second enable signal of a second voltage is applied, wherein the second type first MOS transistor has a better sensing ability than the second type second MOS transistor; and a second type second sense amplifier serially connected between the bit line and the inverted bit line and having a second type third MOS transistor sensing the inverted bit line and a second type fourth MOS transistor sensing the bit line if a third enable signal of the second voltage is applied, wherein the second type fourth MOS transistor has a better sensing ability than the second type third MOS transistor.
摘要翻译：公开了一种半导体存储器件及其位线检测方法。半导体存储器件包括连接在由第一地址和反向位线访问的第一字线之间的第一存储器单元; 连接在由第二地址访问的第二字线和位线之间的第二存储器单元; 第一类型读出放大器串联连接在位线和反相位线之间，并且具有感测反向位线的第一类型第一MOS晶体管和感测位线的第一类型第二MOS晶体管，如果第一电压的第一使能信号为应用; 串联连接在位线和反相位线之间的第二类型的第一读出放大器，并且具有检测反相位线的第二类型的第一MOS晶体管和感测位线的第二类型的第二MOS晶体管，如果第二电压的第二使能信号其中所述第二类型的第一MOS晶体管具有比所述第二类型的第二MOS晶体管更好的感测能力; 以及第二类型的第二读出放大器，其串联连接在位线和反相位线之间，并且具有感测反转位线的第二类型的第三MOS晶体管和感测位线的第二类型的第四MOS晶体管，如果第二个施加电压，其中第二类型的第四MOS晶体管具有比第二类型的第三MOS晶体管更好的感测能力。

4. 发明申请

US20080144414A1 Semiconductor Memory Devices and Method of Sensing Bit Line Thereof 有权
标题翻译：半导体存储器件及其位线检测方法
公开(公告)号：US20080144414A1
公开(公告)日：2008-06-19
申请号：US12021762
申请日：2008-01-29
申请人： Hyun Seok Lee , Jong-Hyun Choi , Ki-Chul Chun , Jong-Eon Lee
发明人： Hyun Seok Lee , Jong-Hyun Choi , Ki-Chul Chun , Jong-Eon Lee
IPC分类号： G11C7/06
CPC分类号： G11C7/065 , G11C11/406 , G11C11/4091 , G11C2211/4065
摘要： A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. This electrically coupling is provided so that each of the first pair of MOS transistors has a first source/drain terminal electrically connected to a corresponding one of the pair of sense bit lines and the second source/drain terminals of the first pair of MOS transistors are electrically connected together. The first pair of MOS transistors of first conductivity type is configured to have different threshold voltages or support different threshold voltage biasing. The second MOS sense amplifier has a first pair of MOS transistors of second conductivity type therein, which are electrically coupled across the pair of sense bit lines.
摘要翻译：感测放大器包括一对感测位线和第一和第二MOS读出放大器。第一MOS读出放大器在其中具有第一导电类型的第一对MOS晶体管，其电耦合在该对感测位线之间。该电耦合被提供为使得第一对MOS晶体管中的每一个具有电连接到该对感测位线中的相应一个和第一对MOS晶体管的第二源极/漏极端子的第一源极/漏极端子电连接在一起。第一导电类型的第一对MOS晶体管被配置为具有不同的阈值电压或支持不同的阈值电压偏置。第二MOS读出放大器具有第一对第二导电类型的MOS晶体管，它们在一对感测位线之间电耦合。

5. 发明授权

US07259978B2 Semiconductor memory devices and signal line arrangements and related methods 失效
标题翻译：半导体存储器件和信号线布置及相关方法
公开(公告)号：US07259978B2
公开(公告)日：2007-08-21
申请号：US11221684
申请日：2005-09-08
申请人： Chul-Woo Park , Jung-Bae Lee , Young-Sun Min , Jong-Hyun Choi , Jong-Eon Lee
发明人： Chul-Woo Park , Jung-Bae Lee , Young-Sun Min , Jong-Hyun Choi , Jong-Eon Lee
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/18 , G11C8/14
摘要： A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.
摘要翻译：半导体存储器件可以包括存储单元阵列，位线读出放大器，子字线驱动器和电极。存储单元阵列可以包括连接在子字线和位线对之间并具有响应于发送到子字线和列选择信号线的信号而被选择的存储器单元的子存储单元阵列。位线读出放大器可以被配置为感测和放大位线对的数据。子字线驱动器可以被配置为组合从字选择信号线发送的信号和从主字线发送的信号，以选择子字线。此外，存储单元阵列可以被配置为在位线对和本地数据线对之间传输数据，并且在本地数据线对和全局数据线对之间传送数据。电极可以被配置为覆盖整个存储单元阵列并施加存储单元所需的电压。局部数据线对可以以与子字线相同的方向布置在电极上方的第一层上。列选择信号线和全局数据线对可以以与位线相同的方向布置在电极上方的第二层上。字选择信号线和主字线可以沿与子字线相同的方向布置在电极上方的第三层上。还讨论了信号线布置的相关方法。

6. 发明授权

US06452828B1 Dynamic random access memory (DRAM) having a structure for emplying a word line low voltage 有权
公开(公告)号：US06452828B1
公开(公告)日：2002-09-17
申请号：US09886202
申请日：2001-06-20
申请人： Sang-Seok Kang , Jong-Hyun Choi , Jong-Eon Lee
发明人： Sang-Seok Kang , Jong-Hyun Choi , Jong-Eon Lee
IPC分类号： G11C506
CPC分类号： G11C11/4085 , G11C8/08
摘要： Disclosed is a dynamic random access memory (DRAM) device having word line low voltage supply lines for driving word lines in a mesh structure. The DRAM device includes a plurality of cell arrays each of which is formed of memory cells coupled to word lines and bit lines in a matrix. The memory device further includes regions of sense amplifiers disposed between the cell arrays arranged along the row direction, regions of word line drivers disposed between the cell arrays arranged along the column direction, conjunction regions disposed at positions adjacent to the regions of the sense amplifiers and word line drivers, and a plurality of word line low voltage supply lines disposed on the conjunction regions. The word line low voltage supply lines are electrically interconnected for each other at least on the conjunction regions. According to the layout arrangement, loadings of the word line low voltage supply lines are almost equally distributed, and thereby word line low noise are decreased.

7. 发明申请

US20060056218A1 Semiconductor memory devices and signal line arrangements and related methods 失效
标题翻译：半导体存储器件和信号线布置及相关方法
公开(公告)号：US20060056218A1
公开(公告)日：2006-03-16
申请号：US11221684
申请日：2005-09-08
申请人： Chul-Woo Park , Jung-Bae Lee , Young-Sun Min , Jong-Hyun Choi , Jong-Eon Lee
发明人： Chul-Woo Park , Jung-Bae Lee , Young-Sun Min , Jong-Hyun Choi , Jong-Eon Lee
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/18 , G11C8/14
摘要： A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.
摘要翻译：半导体存储器件可以包括存储单元阵列，位线读出放大器，子字线驱动器和电极。存储单元阵列可以包括连接在子字线和位线对之间并具有响应于发送到子字线和列选择信号线的信号而被选择的存储器单元的子存储单元阵列。位线读出放大器可以被配置为感测和放大位线对的数据。子字线驱动器可以被配置为组合从字选择信号线发送的信号和从主字线发送的信号，以选择子字线。此外，存储单元阵列可以被配置为在位线对和本地数据线对之间传输数据，并且在本地数据线对和全局数据线对之间传送数据。电极可以被配置为覆盖整个存储单元阵列并施加存储单元所需的电压。局部数据线对可以以与子字线相同的方向布置在电极上方的第一层上。列选择信号线和全局数据线对可以以与位线相同的方向布置在电极上方的第二层上。字选择信号线和主字线可以沿着与子字线相同的方向布置在电极上方的第三层上。还讨论了信号线布置的相关方法。

8. 发明授权

US08963130B2 Transparent electrode and organic light emitting diode device including the transparent electrode and method of manufacturing the same 有权
标题翻译：包括透明电极的透明电极和有机发光二极管器件及其制造方法
公开(公告)号：US08963130B2
公开(公告)日：2015-02-24
申请号：US13108457
申请日：2011-05-16
申请人： Jong-Hyun Choi
发明人： Jong-Hyun Choi
IPC分类号： H01L29/08 , H01L35/24 , H01L51/00 , H01L29/04 , H01L29/10 , H01L31/00 , H01J1/62 , H01J63/04 , H01L27/12 , H01L51/52
CPC分类号： H01L27/124 , H01L51/5215 , H01L51/5265 , H01L2227/323
摘要： Disclosed are a transparent electrode including a first light-transmission layer, a metal layer, and a second light-transmission layer sequentially formed, an organic light emitting device including the transparent electrode, and a method of manufacturing the same. The second light-transmission layer includes a conductive oxide and a metal catalyst.
摘要翻译：公开了包括依次形成的第一透光层，金属层和第二透光层的透明电极，包括透明电极的有机发光器件及其制造方法。第二透光层包括导电氧化物和金属催化剂。

9. 发明授权

US08575609B2 Organic light emitting display apparatus and method of manufacturing the same 有权
标题翻译：有机发光显示装置及其制造方法
公开(公告)号：US08575609B2
公开(公告)日：2013-11-05
申请号：US13200826
申请日：2011-10-03
申请人： Jong-Hyun Choi
发明人： Jong-Hyun Choi
IPC分类号： H01L29/04
CPC分类号： H01L27/3265 , H01L27/3258
摘要： An organic light emitting display apparatus includes a substrate, a thin film transistor formed on the substrate and comprising an active layer, a gate electrode, a source electrode, and a drain electrode, a first gate insulation layer arranged between the gate electrode and the active layer and including an opening portion, a first electrode arranged between the substrate and the first gate insulation layer to overlap the opening portion, an intermediate layer formed on the first electrode and including an organic light emitting layer, a second electrode formed on the intermediate layer, and a capacitor including a first capacitor electrode that is arranged between the substrate and the first gate insulation layer and a second capacitor electrode that is arranged on an upper surface of the first gate insulation layer.
摘要翻译：一种有机发光显示装置，包括：基板，形成在基板上的薄膜晶体管，具有有源层，栅电极，源电极和漏电极，配置在栅电极和活性层之间的第一栅极绝缘层并且包括开口部分，布置在所述基板和所述第一栅极绝缘层之间以与所述开口部分重叠的第一电极，形成在所述第一电极上并包括有机发光层的中间层，形成在所述中间层上的第二电极以及电容器，其包括布置在所述基板和所述第一栅极绝缘层之间的第一电容器电极和布置在所述第一栅极绝缘层的上表面上的第二电容器电极。

10. 发明申请

US20130288413A1 ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：有机发光显示装置及其制造方法
公开(公告)号：US20130288413A1
公开(公告)日：2013-10-31
申请号：US13928120
申请日：2013-06-26
申请人： Jong-Hyun Choi , Jong-Yun Kim , Jin-Goo Kang , Dae-Hyun Noh
发明人： Jong-Hyun Choi , Jong-Yun Kim , Jin-Goo Kang , Dae-Hyun Noh
IPC分类号： H01L51/56
CPC分类号： H01L51/56 , H01L27/3246
摘要： An organic light-emitting display device including a substrate; at least one thin-film transistor (TFT) formed on the substrate; a planarizing layer covering the TFT; a pixel electrode, which is formed on the planarizing layer and is connected to the TFT; a protective layer surrounding an edge of the pixel electrode; a pixel defining layer (PDL), which has an overhang (OH) structure protruding more than the top surface of the protective layer, covers the protective layer and the edge of the pixel electrode, and exposes a portion of the pixel electrode surrounded by the protective layer; a counter electrode facing the pixel electrode; and an intermediate layer, which is interposed between the pixel electrode and the counter electrode and includes a light-emitting layer and at least one organic layer, where the thickness of the intermediate layer is greater than the thickness of the protective layer.
摘要翻译：一种有机发光显示装置，包括：基板; 在所述基板上形成的至少一个薄膜晶体管（TFT）; 覆盖TFT的平坦化层; 像素电极，其形成在平坦化层上并连接到TFT; 围绕像素电极的边缘的保护层; 具有比保护层的顶表面突出的突出（OH）结构的像素限定层（PDL）覆盖保护层和像素电极的边缘，并且暴露由像素电极包围的像素电极的一部分保护层; 面对像素电极的对置电极; 以及中间层，其介于像素电极和对电极之间，并且包括发光层和至少一个有机层，其中中间层的厚度大于保护层的厚度。

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