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    • 5. 发明申请
    • FLIP-FLOP CIRCUIT AND SCAN FLIP-FLOP CIRCUIT
    • FLIP-FLOP电路和扫描FLIP-FLOP电路
    • US20110231723A1
    • 2011-09-22
    • US13049427
    • 2011-03-16
    • Hyoung-Wook LEEMin-Su KimChung-Hee KimJin-Soo Park
    • Hyoung-Wook LEEMin-Su KimChung-Hee KimJin-Soo Park
    • G01R31/3177G06F11/25
    • G06F11/24
    • A scan flip-flop circuit includes a pulse generator, a dynamic input unit and a latch output unit. The pulse generator generates a pulse signal which is enabled in synchronization with a rising edge of a clock signal in a normal mode, and is selectively enabled in synchronization with the rising edge of the clock signal in response to a logic level of a scan input signal in a scan mode. The dynamic input unit precharges a first node to a power supply voltage in a first phase of the clock signal, selectively discharges the first node in the normal mode, and discharges the first node in the scan mode. The latch output unit latches an internal signal provided from the first node to provide an output data, and determines whether the output data is toggled based on the clock signal and a previous state of the output data.
    • 扫描触发电路包括脉冲发生器,动态输入单元和锁存器输出单元。 脉冲发生器产生脉冲信号,其在正常模式下与时钟信号的上升沿同步使能,并且响应于扫描输入信号的逻辑电平而与时钟信号的上升沿同步地选择性地使能 处于扫描模式。 动态输入单元在时钟信号的第一阶段中将第一节点预充电到电源电压,以正常模式选择性地放电第一节点,并以扫描模式放电第一节点。 闩锁输出单元锁存从第一节点提供的内部信号以提供输出数据,并且基于时钟信号和输出数据的先前状态来确定输出数据是否被切换。
    • 8. 发明申请
    • FINITE IMPULSE RESPONSE (FIR) FILTER WITHOUT DECIMATION
    • 有限冲突响应(FIR)滤波器,不带十进制
    • US20090327793A1
    • 2009-12-31
    • US12355182
    • 2009-01-16
    • Jin-hyun KimJin-Soo ParkHyung-sun LimHan-Woong YooYoung-Eil KimBum-Man KimChang-Joon Park
    • Jin-hyun KimJin-Soo ParkHyung-sun LimHan-Woong YooYoung-Eil KimBum-Man KimChang-Joon Park
    • G06F17/10G06F1/06
    • H03H15/023
    • Provided is a discrete signal finite impulse response (FIR) filter and a filter set in which a plurality of FIR filter units are connected in a cascade structure to remove down-sampling by decimation, in order to improve the attenuation characteristics of a FIR filter, such as, for example, a switched capacitor filter. The FIR filter includes a clock generator generating a plurality of clock signals that are different from each other; and N+2 sub blocks each including N sample storage units, each sample storage unit storing a received sample. Each sub block being in a state among a number of possible states including N charging states for storing the received sample, a transfer state for outputting the stored sample and a reset state for operation initialization. The N charging states, the transfer state and the reset state are changed sequentially in response to the clock signals.
    • 提供了一种离散信号有限脉冲响应(FIR)滤波器和滤波器组,其中多个FIR滤波器单元以级联结构连接以通过抽取来去除下采样,以便提高FIR滤波器的衰减特性, 例如开关电容滤波器。 FIR滤波器包括产生彼此不同的多个时钟信号的时钟发生器; 和N + 2个子块,每个子块包括N个采样存储单元,每个采样存储单元存储接收的采样。 每个子块处于包括用于存储所接收的采样的N个充电状态,用于输出所存储的采样的传送状态和用于操作初始化的复位状态的多个可能状态之间的状态。 响应于时钟信号,N个充电状态,传送状态和复位状态顺序地改变。