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    • 7. 发明申请
    • NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    • 非易失性存储器件及其操作方法
    • US20100008142A1
    • 2010-01-14
    • US12493299
    • 2009-06-29
    • Sung Hyun Jung
    • Sung Hyun Jung
    • G11C16/04G11C16/06
    • G11C16/3459G11C16/3454
    • A nonvolatile memory device comprises a page buffer unit, first to kth logic combination units, and a control unit. The page buffer unit includes first to Nth page buffer blocks. N and k are natural numbers. Each of the first to Nth page buffer blocks comprises m page buffers, divided into first to kth page buffer groups, and first to kth pass/fail check units configured to output respective verification signals, each indicative of a program pass or a program fail, according to data stored in latches of the page buffers included in each of the page buffer groups. The first to kth logic combination units are each configured to output respective first to kth pass/fail determination signals.
    • 非易失性存储器件包括页缓冲器单元,第一至第K逻辑组合单元和控制单元。 页缓冲器单元包括第一到第N页缓冲块。 N和k是自然数。 第一到第N页缓冲块中的每一个包括被分成第一到第k页缓冲器组的m页缓冲器和被配置为输出各自的验证信号的第一到第k个通过/失败检查单元,每个验证信号指示程序通过或程序失败, 根据存储在每个页面缓冲器组中的页面缓冲器的锁存器中的数据。 第一至第k逻辑组合单元被配置为输出相应的第一至第k个通过/不合格确定信号。
    • 9. 发明授权
    • Nonvolatile memory device and method of operating the same
    • 非易失存储器件及其操作方法
    • US07872941B2
    • 2011-01-18
    • US12493299
    • 2009-06-29
    • Sung Hyun Jung
    • Sung Hyun Jung
    • G11C13/04
    • G11C16/3459G11C16/3454
    • A nonvolatile memory device comprises a page buffer unit, first to kth logic combination units, and a control unit. The page buffer unit includes first to Nth page buffer blocks. N and k are natural numbers. Each of the first to Nth page buffer blocks comprises m page buffers, divided into first to kth page buffer groups, and first to kth pass/fail check units configured to output respective verification signals, each indicative of a program pass or a program fail, according to data stored in latches of the page buffers included in each of the page buffer groups. The first to kth logic combination units are each configured to output respective first to kth pass/fail determination signals.
    • 非易失性存储器件包括页缓冲器单元,第一至第K逻辑组合单元和控制单元。 页缓冲器单元包括第一到第N页缓冲块。 N和k是自然数。 第一到第N页缓冲块中的每一个包括被分成第一到第k页缓冲器组的m页缓冲器和被配置为输出各自的验证信号的第一到第k个通过/失败检查单元,每个验证信号指示程序通过或程序失败, 根据存储在每个页面缓冲器组中的页面缓冲器的锁存器中的数据。 第一至第k逻辑组合单元被配置为输出相应的第一至第k个通过/不合格确定信号。