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1. 发明授权

US07205799B2 Input buffer having a stabilized operating point and an associated method 失效
标题翻译：输入缓冲器具有稳定的工作点和相关联的方法
公开(公告)号：US07205799B2
公开(公告)日：2007-04-17
申请号：US11225915
申请日：2005-09-13
申请人： Hyun-Jin Kim , Seong-Jin Jang , Kwang-II Park , Sang-Joon Hwang , Ho-Young Song , Ho-Kyong Lee , Woo-Jin Lee
发明人： Hyun-Jin Kim , Seong-Jin Jang , Kwang-II Park , Sang-Joon Hwang , Ho-Young Song , Ho-Kyong Lee , Woo-Jin Lee
IPC分类号： H03K3/00
CPC分类号： H03F3/45
摘要： We describe an input buffer having a stabilized operating point and an associated method. An input buffer may include a first differential amplifying unit to generate a first output signal having a first operating point and a second differential amplifying unit to generate a second output signal having a second operating point. An output control circuit varies respective weights of the first and second output signals responsive to an output control signal. The first differential amplifying unit may operate responsive to a reference voltage and an input voltage signal. The second differential amplifying unit may operate responsive to the reference voltage and the input voltage signal. The first operating point may be relatively higher than the second operating point.
摘要翻译：我们描述具有稳定的工作点和相关方法的输入缓冲器。输入缓冲器可以包括第一差分放大单元，用于产生具有第一工作点的第一输出信号和第二差分放大单元，以产生具有第二工作点的第二输出信号。响应于输出控制信号，输出控制电路改变第一和第二输出信号的各个权重。第一差分放大单元可以响应于参考电压和输入电压信号而进行操作。第二差分放大单元可以响应于参考电压和输入电压信号而工作。第一工作点可以相对高于第二工作点。

2. 发明申请

US20060066364A1 Input buffer having a stabilized operating point and an associated method 失效
标题翻译：输入缓冲器具有稳定的工作点和相关联的方法
公开(公告)号：US20060066364A1
公开(公告)日：2006-03-30
申请号：US11225915
申请日：2005-09-13
申请人： Hyun-Jin Kim , Seong-Jin Jang , Kwang-Il Park , Sang-Joon Hwang , Ho-Young Song , Ho-Kyong Lee , Woo-Jin Lee
发明人： Hyun-Jin Kim , Seong-Jin Jang , Kwang-Il Park , Sang-Joon Hwang , Ho-Young Song , Ho-Kyong Lee , Woo-Jin Lee
IPC分类号： H03B1/00
CPC分类号： H03F3/45
摘要： We describe an input buffer having a stabilized operating point and an associated method. An input buffer may include a first differential amplifying unit to generate a first output signal having a first operating point and a second differential amplifying unit to generate a second output signal having a second operating point. An output control circuit varies respective weights of the first and second output signals responsive to an output control signal. The first differential amplifying unit may operate responsive to a reference voltage and an input voltage signal. The second differential amplifying unit may operate responsive to the reference voltage and the input voltage signal. The first operating point may be relatively higher than the second operating point.
摘要翻译：我们描述具有稳定的工作点和相关方法的输入缓冲器。输入缓冲器可以包括：第一差分放大单元，用于产生具有第一工作点的第一输出信号和第二差分放大单元，以产生具有第二工作点的第二输出信号。响应于输出控制信号，输出控制电路改变第一和第二输出信号的各个权重。第一差分放大单元可以响应于参考电压和输入电压信号而进行操作。第二差分放大单元可以响应于参考电压和输入电压信号而工作。第一工作点可以相对高于第二工作点。

3. 发明申请

US20100091600A1 CIRCUIT AND METHOD FOR SAMPLING VALID COMMAND USING EXTENDED VALID ADDRESS WINDOW IN DOUBLE PUMPED ADDRESS SCHEME MEMORY DEVICE 审中-公开
标题翻译：在双重抽取地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法
公开(公告)号：US20100091600A1
公开(公告)日：2010-04-15
申请号：US12635785
申请日：2009-12-11
申请人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
发明人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
IPC分类号： G11C8/00 , G11C8/18
CPC分类号： G06F12/02 , G11C7/1078 , G11C7/109
摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
摘要翻译：提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

4. 发明授权

US07656742B2 Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device 有权
标题翻译：在双泵浦地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法
公开(公告)号：US07656742B2
公开(公告)日：2010-02-02
申请号：US12128464
申请日：2008-05-28
申请人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
发明人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
IPC分类号： G11C8/00
CPC分类号： G06F12/02 , G11C7/1078 , G11C7/109
摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
摘要翻译：提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

5. 发明授权

US07394720B2 Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device 有权
标题翻译：在双泵浦地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法
公开(公告)号：US07394720B2
公开(公告)日：2008-07-01
申请号：US11560746
申请日：2006-11-16
申请人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
发明人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
IPC分类号： G11C8/00
CPC分类号： G06F12/02 , G11C7/1078 , G11C7/109
摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
摘要翻译：提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

6. 发明申请

US20110208988A1 Latency signal generator and method thereof 审中-公开
标题翻译：延迟信号发生器及其方法
公开(公告)号：US20110208988A1
公开(公告)日：2011-08-25
申请号：US13064961
申请日：2011-04-28
申请人： Hyun-Jin Kim , Ho-young Song , Seong-Jin Jang , Youn-sik Park
发明人： Hyun-Jin Kim , Ho-young Song , Seong-Jin Jang , Youn-sik Park
IPC分类号： G06F1/04
CPC分类号： G11C7/22 , G11C7/222
摘要： A latency signal generator and method thereof are provided. The example latency signal generator may include a sampling clock signal generator adjusting a plurality of initial sampling clock signals based on a received clock signal to generate a plurality of adjusted sampling clock signals, a latch enable signal supply unit adjusting a plurality of initial latch enable signals based on a given one of the plurality of initial sampling clock signals to generate a plurality of adjusted latch enable signals and a latch unit including a plurality of latency latches, each of the plurality of latency latches selectively latching a given internal read command based on one of the plurality of adjusted sampling clock signals and one of the plurality of adjusted latch enable signals.
摘要翻译：提供了一种等待时间信号发生器及其方法。示例性延迟信号发生器可以包括采样时钟信号发生器，其基于所接收的时钟信号来调整多个初始采样时钟信号，以产生多个经调整的采样时钟信号;锁存使能信号供应单元，调整多个初始锁存使能信号基于所述多个初始采样时钟信号中的给定一个以产生多个调整的锁存使能信号，以及包括多个延迟锁存器的锁存单元，所述多个延迟锁存器中的每一个基于一个等待锁存器选择性地锁存给定的内部读取命令多个经调整的采样时钟信号中的一个和多个调整的锁存使能信号中的一个。

7. 发明授权

US07463072B2 Small swing signal receiver for low power consumption and semiconductor device including the same 有权
标题翻译：用于低功耗的小型摆动信号接收器和包括它的半导体器件
公开(公告)号：US07463072B2
公开(公告)日：2008-12-09
申请号：US11566651
申请日：2006-12-04
申请人： Hyun-Jin Kim , Seong-Jin Jang , Kwang-Il Park , Woo-Jin Lee
发明人： Hyun-Jin Kim , Seong-Jin Jang , Kwang-Il Park , Woo-Jin Lee
IPC分类号： H03B1/00
CPC分类号： H03K19/0013 , H03K19/018521
摘要： A circuit including a voltage boost circuit coupled to a first node and a second node, and configured to apply a boosted first node voltage to the second node; and an inverter circuit coupled to the first node, the second node, and a third node, and configured to generate a signal on the third node in response to the signals on the first node and the second node.
摘要翻译：一种电路，包括耦合到第一节点和第二节点的升压电路，并且被配置为将升压的第一节点电压施加到所述第二节点; 以及反相器电路，其耦合到所述第一节点，所述第二节点和第三节点，并且被配置为响应于所述第一节点和所述第二节点上的信号而在所述第三节点上生成信号。

8. 发明授权

US07420387B2 Semiconductor device capable of controlling OCD and ODT circuits and control method used by the semiconductor device 有权
标题翻译：能够控制OCD和ODT电路的半导体器件和半导体器件使用的控制方法
公开(公告)号：US07420387B2
公开(公告)日：2008-09-02
申请号：US11402123
申请日：2006-04-11
申请人： Woo-Jin Lee , Kwang-Il Park , Hyun-Jin Kim , Seong-Jin Jang
发明人： Woo-Jin Lee , Kwang-Il Park , Hyun-Jin Kim , Seong-Jin Jang
IPC分类号： H03K17/16
CPC分类号： H03K19/0005
摘要： Provided is a semiconductor device capable of controlling an on-die-termination (ODT) circuit and an off-chip-driver (OCD) circuit and a control method used by the semiconductor device. The semiconductor device includes a control code generation unit generating a control code in response to a control signal, an addition unit adding an adjustment code to the control code to produce an adjusted control code, and an ODT circuit, wherein an impedance of the ODT circuit is adjusted in response to the adjusted control code. The semiconductor device can adjust the control code more precisely by adding or subtracting the adjustment code to or from the control code. Accordingly, the impedance of an OCD circuit or ODT circuit can be adjusted more precisely.
摘要翻译：提供了能够控制芯片上终端（ODT）电路和芯片外驱动器（OCD）电路的半导体器件以及由半导体器件使用的控制方法。半导体器件包括响应于控制信号产生控制代码的控制代码生成单元，向控制代码添加调整代码以产生调整后的控制代码的加法单元和ODT电路，其中ODT电路的阻抗根据调整后的控制代码进行调整。半导体器件可以通过向或从控制代码添加或减去调整代码来更精确地调整控制代码。因此，可以更精确地调整OCD电路或ODT电路的阻抗。

9. 发明申请

US20060226868A1 Semiconductor device capable of controlling OCD and ODT circuits and control method used by the semiconductor device 有权
标题翻译：能够控制OCD和ODT电路的半导体器件和半导体器件使用的控制方法
公开(公告)号：US20060226868A1
公开(公告)日：2006-10-12
申请号：US11402123
申请日：2006-04-11
申请人： Woo-Jin Lee , Kwang-Il Park , Hyun-Jin Kim , Seong-Jin Jang
发明人： Woo-Jin Lee , Kwang-Il Park , Hyun-Jin Kim , Seong-Jin Jang
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： Provided is a semiconductor device capable of controlling an on-die-termination (ODT) circuit and an off-chip-driver (OCD) circuit and a control method used by the semiconductor device. The semiconductor device includes a control code generation unit generating a control code in response to a control signal, an addition unit adding an adjustment code to the control code to produce an adjusted control code, and an ODT circuit, wherein an impedance of the ODT circuit is adjusted in response to the adjusted control code. The semiconductor device can adjust the control code more precisely by adding or subtracting the adjustment code to or from the control code. Accordingly, the impedance of an OCD circuit or ODT circuit can be adjusted more precisely.
摘要翻译：提供了能够控制芯片上终端（ODT）电路和芯片外驱动器（OCD）电路的半导体器件以及由半导体器件使用的控制方法。半导体器件包括响应于控制信号产生控制代码的控制代码生成单元，向控制代码添加调整代码以产生调整后的控制代码的加法单元和ODT电路，其中ODT电路的阻抗根据调整后的控制代码进行调整。半导体器件可以通过向或从控制代码添加或减去调整代码来更精确地调整控制代码。因此，可以更精确地调整OCD电路或ODT电路的阻抗。

10. 发明申请

US20070069213A1 Flexible adjustment of on-die termination values in semiconductor device 审中-公开
标题翻译：灵活调整半导体器件中的片上端接值
公开(公告)号：US20070069213A1
公开(公告)日：2007-03-29
申请号：US11475668
申请日：2006-06-27
申请人： Woo-Jin Lee , Kwang-Il Park , Hyun-Jin Kim
发明人： Woo-Jin Lee , Kwang-Il Park , Hyun-Jin Kim
IPC分类号： H01L27/108 , H01L29/00 , H01L31/036 , H01L31/112
CPC分类号： G11C7/02 , G11C7/1048 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2207/2254
摘要： A termination value for a pin of a semiconductor device is set to a first value if a pin signal has a first logic state at an edge of a control signal, and to a second value if the pin signal has a second logic state at the edge of the control signal. Alternatively, a respective logic state of a first control signal is determined at an edge of a second control signal, and a respective logic state of the pin signal is determined at the edge of the second control signal. The termination value is set depending on such respective logic states.
摘要翻译：如果引脚信号在控制信号的边缘处具有第一逻辑状态，则半导体器件的引脚的终止值被设置为第一值，并且如果引脚信号在边沿处具有第二逻辑状态，则将第二值设置为第二值的控制信号。或者，在第二控制信号的边缘确定第一控制信号的相应逻辑状态，并且在第二控制信号的边缘确定引脚信号的相应逻辑状态。终止值根据这些各自的逻辑状态来设定。

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