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1. 发明授权

US07704814B2 Method for manufacturing MOS transistor of semiconductor device 失效
标题翻译：制造半导体器件的MOS晶体管的方法
公开(公告)号：US07704814B2
公开(公告)日：2010-04-27
申请号：US11498680
申请日：2006-08-02
申请人： Hyun Soo Shin , Jae Won Han
发明人： Hyun Soo Shin , Jae Won Han
IPC分类号： H01L21/336
CPC分类号： H01L21/823493 , H01L29/6659 , H01L29/7833
摘要： Disclosed is a method for manufacturing a semiconductor device including a low-voltage MOS transistor and a high-voltage MOS transistor. The present method includes a low-voltage well implantation process on a semiconductor substrate to form a first well in a first region of the substrate and a second well in a second region of the substrate; forming first and second gate oxide layers and first and second gate electrodes in the first and second regions, respectively; forming a first photoresist pattern to expose the first region; forming a first LDD region in the first region exposed by the first photoresist pattern and the first gate electrode; removing the first photoresist pattern; forming a second photoresist pattern to expose the second region; forming a second LDD region in the second region exposed by the second photoresist pattern and the second gate electrode; performing a compensational implantation on the second region to adjust a well concentration for the high-voltage MOS transistor; and removing the second photoresist pattern.
摘要翻译：公开了一种制造包括低电压MOS晶体管和高压MOS晶体管的半导体器件的方法。本方法包括在半导体衬底上的低电压阱注入工艺，以在衬底的第一区域中形成第一阱，在衬底的第二区域中形成第二阱; 分别在第一和第二区域中形成第一和第二栅极氧化物层和第一和第二栅电极; 形成第一光致抗蚀剂图案以暴露第一区域; 在由第一光致抗蚀剂图案和第一栅电极暴露的第一区域中形成第一LDD区; 去除第一光致抗蚀剂图案; 形成第二光致抗蚀剂图案以暴露所述第二区域; 在由所述第二光致抗蚀剂图案和所述第二栅电极暴露的所述第二区域中形成第二LDD区域; 在所述第二区域上执行补偿注入以调整所述高压MOS晶体管的阱浓度; 并且去除第二光致抗蚀剂图案。

2. 发明授权

US07598583B2 Image sensor 失效
标题翻译：图像传感器
公开(公告)号：US07598583B2
公开(公告)日：2009-10-06
申请号：US11782144
申请日：2007-07-24
申请人： Jae Won Han
发明人： Jae Won Han
IPC分类号： H01L31/02
CPC分类号： H01L27/14634 , H01L27/14621 , H01L27/14627 , H01L27/1469 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An image sensor according to embodiments may include a first substrate having photodiode cells, a second substrate having a logic circuit, and connection electrodes that may electrically connect the photodiode cells with the logic circuit. In embodiments, more area may be available on the first substrate for photodiode cells and light loss may be reduced.
摘要翻译：根据实施例的图像传感器可以包括具有光电二极管单元的第一基板，具有逻辑电路的第二基板以及可以将光电二极管单元与逻辑电路电连接的连接电极。在实施例中，用于光电二极管单元的第一基板上可能有更多的区域可用，并且可以减少光损失。

3. 发明授权

US07541279B2 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07541279B2
公开(公告)日：2009-06-02
申请号：US11615105
申请日：2006-12-22
申请人： Sang Chul Kim , Jae Won Han
发明人： Sang Chul Kim , Jae Won Han
IPC分类号： H01L21/20
CPC分类号： H01L21/76874 , C25D3/38 , C25D3/58 , C25D5/022 , C25D7/123 , H01L21/2885 , H01L21/76877
摘要： A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first metal on an inner surface of the contact hole, submerging the semiconductor substrate on which the first metal is deposited into an electrochemical plating (ECP) solution bath in which a second metal is dissolved, dissolving the first metal in the ECP solution bath, plating the first and second metals dissolved in the ECP solution bath at the same time to gap-fill an alloy of the first and second metals in the contact hole, and removing the alloy using the interlayer insulating layer as an end point in a CMP process to form an alloy interconnection.
摘要翻译：提供一种制造半导体器件的方法。该方法包括以下步骤：在半导体衬底上形成层间绝缘层，选择性地图案化层间绝缘层以形成接触孔;在接触孔的内表面上沉积第一金属;浸没第一金属沉积到其中溶解有第二金属的电化学电镀（ECP）溶液浴中，将第一金属溶解在ECP溶液浴中，同时电镀溶解在ECP溶液浴中的第一和第二金属以间隙填充接触孔中的第一和第二金属的合金，并且在CMP工艺中使用层间绝缘层作为终点去除合金以形成合金互连。

4. 发明授权

US08593415B2 Method for processing touch signal in mobile terminal and mobile terminal using the same 有权
标题翻译：用于处理移动终端中的触摸信号的方法和使用其的移动终端
公开(公告)号：US08593415B2
公开(公告)日：2013-11-26
申请号：US12720620
申请日：2010-03-09
申请人： Jae Won Han , Min Kyu Ha
发明人： Jae Won Han , Min Kyu Ha
IPC分类号： G09G5/00
CPC分类号： G06F1/1694 , G06F3/0346 , G06F3/04883
摘要： A method for processing a touch signal in a mobile terminal and a mobile terminal using the same are disclosed, wherein the method comprises: detecting a shaking of a mobile terminal by using a mobile terminal shaking detection sensor within a predetermined time from a touched time while a touch screen is being touched; and outputting an output signal based on the detected shaking.
摘要翻译：公开了一种用于处理移动终端中的触摸信号的方法和使用该触摸信号的移动终端的方法，其中该方法包括：在触摸时间的预定时间内通过使用移动终端抖动检测传感器来检测移动终端的振动，同时正在触摸一个触摸屏; 并且基于检测到的抖动输出输出信号。

5. 发明授权

US07745250B2 Image sensor and method for manufacturing the same 有权
标题翻译：图像传感器及其制造方法
公开(公告)号：US07745250B2
公开(公告)日：2010-06-29
申请号：US11964415
申请日：2007-12-26
申请人： Jae Won Han
发明人： Jae Won Han
IPC分类号： H01L29/72
CPC分类号： H01L27/14634 , H01L27/1469
摘要： An image sensor and manufacturing process thereof are provided. An image sensor according to an embodiment comprises a first wafer formed with a photodiode cell without a microlens and a second wafer formed with a circuit part including transistor and a capacitor. The first wafer is stacked on the second wafer such that a connecting electrode can be used to electrically connect the photodiode cell of the first wafer to the circuit part of the second wafer.
摘要翻译：提供了一种图像传感器及其制造方法。根据实施例的图像传感器包括形成有没有微透镜的光电二极管单元的第一晶片和形成有包括晶体管和电容器的电路部分的第二晶片。第一晶片被堆叠在第二晶片上，使得可以使用连接电极将第一晶片的光电二极管电池与第二晶片的电路部分电连接。

6. 发明授权

US07683489B2 Semiconductor device and fabricating method thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07683489B2
公开(公告)日：2010-03-23
申请号：US11849102
申请日：2007-08-31
申请人： Kyung Min Park , Jae Won Han
发明人： Kyung Min Park , Jae Won Han
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/1461 , H01L2924/00 , H01L2224/05599 , H01L2224/0556
摘要： A semiconductor device and a fabricating method thereof are provided. A PMD layer and at least one IMD layer are formed on a semiconductor substrate. A through-electrode penetrates through the PMD layer and the IMD layer, and a connecting electrode connects to the through-electrode.
摘要翻译：提供了一种半导体器件及其制造方法。在半导体衬底上形成PMD层和至少一个IMD层。贯通电极穿透PMD层和IMD层，连接电极与贯通电极连接。

7. 发明申请

US20090189283A1 ALUMINUM METAL LINE OF A SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：半导体器件的铝金属线及其制造方法
公开(公告)号：US20090189283A1
公开(公告)日：2009-07-30
申请号：US12351365
申请日：2009-01-09
申请人： Jae Won Han
发明人： Jae Won Han
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/32051 , H01L21/76849 , H01L21/76865 , H01L21/76885
摘要： A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is performed thereon. An intermetallic dielectric layer is applied on the metal line pattern. The first B metal thin layer is removed by a chemical mechanical planarization process to form a first stage metal line. A second aluminum layer and a second metal thin layer are sequentially applied. Photoresist is applied, a photolithography process is performed to form a metal line pattern, and etching is performed to form a second stage metal line. An intermetallic dielectric layer is applied on the second stage metal line. A chemical mechanical planarization process is performed on the second intermetallic dielectric layer.
摘要翻译：一种形成半导体器件的铝线的方法，其中第一A金属薄层，第一铝层和第一B金属薄层依次施加在层间绝缘层上。进行光刻工艺以形成金属线图案，并对其进行蚀刻。在金属线图案上施加金属间介电层。通过化学机械平面化处理去除第一B金属薄层以形成第一级金属线。依次施加第二铝层和第二金属薄层。应用光刻胶，进行光刻工艺以形成金属线图案，并进行蚀刻以形成第二级金属线。在第二级金属线上施加金属间介电层。在第二金属间介电层上进行化学机械平面化处理。

8. 发明授权

US06903026B2 Sputter etch methods 失效
标题翻译：溅射蚀刻方法
公开(公告)号：US06903026B2
公开(公告)日：2005-06-07
申请号：US10875125
申请日：2004-06-23
申请人： Jae Won Han
发明人： Jae Won Han
IPC分类号： H01L21/302 , H01L21/3213
CPC分类号： H01L21/32131
摘要： A sputter etch method in the semiconductor fabrication is disclosed. A sputter etch method for etching a layer on a semiconductor substrate in a chamber by RF plasma, includes loading a substrate for conditioning into the chamber, depositing a metal coating layer on the inside wall of the chamber by sputter etching the substrate for conditioning in the chamber, unloading the substrate for conditioning from the chamber, loading the semiconductor substrate with the layer, and etching the layer on the semiconductor substrate. Accordingly, the sputter etch method can enhance a reliability for a fabrication process of a semiconductor device under the environment of the substantial decrease in impurity falling probability. In other words, the impurity falling probability can be decreased by coating a metal layer on the wall of the sputter etch chamber employing a wafer on which a barrier metal layer is deposited right before a main lot in a sputter etch process.
摘要翻译：公开了半导体制造中的溅射蚀刻方法。用于通过RF等离子体蚀刻腔室中的半导体衬底上的层的溅射蚀刻方法包括将用于调节的衬底加载到腔室中，通过溅射蚀刻衬底以在衬底的内壁中进行调节来在腔室的内壁上沉积金属涂层从所述室中卸载用于调理的基板，将所述半导体基板与所述层一起加载，以及蚀刻所述半导体基板上的所述层。因此，溅射蚀刻方法可以在杂质下降概率显着降低的环境下提高半导体器件的制造工艺的可靠性。换句话说，可以通过在溅射蚀刻室的壁上涂覆金属层，使用其上在溅射蚀刻工艺中在主批次之前沉积阻挡金属层的晶片来降低杂质落下概率。

9. 发明授权

US07743482B2 Fabricating method of a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07743482B2
公开(公告)日：2010-06-29
申请号：US11863407
申请日：2007-09-28
申请人： Jae Won Han
发明人： Jae Won Han
IPC分类号： H04R31/00
CPC分类号： H01L25/16 , H01L23/645 , H01L2924/0002 , H01L2924/19104 , Y10T29/49005 , Y10T29/49069 , Y10T29/49073 , Y10T29/4908 , H01L2924/00
摘要： A semiconductor device and fabricating method thereof are provided. A first substrate with an inductor cell and a through-electrode is connected to a second substrate having an RF device circuit unit. The first substrate can be stacked on the second substrate, and a connecting electrode can electrically connect the inductor cell to the RF device circuit unit.
摘要翻译：提供了一种半导体器件及其制造方法。具有电感器单元和通孔的第一衬底连接到具有RF器件电路单元的第二衬底。第一衬底可以堆叠在第二衬底上，并且连接电极可以将电感器单元电连接到RF器件电路单元。

10. 发明授权

US07368749B2 Method of detecting misalignment of ion implantation area 失效
标题翻译：检测离子注入区域的不对准方法
公开(公告)号：US07368749B2
公开(公告)日：2008-05-06
申请号：US11523961
申请日：2006-09-19
申请人： Jae Won Han
发明人： Jae Won Han
IPC分类号： H01L23/58 , H01L23/544 , H01L29/10
CPC分类号： H01L22/34
摘要： A method of detecting misalignment of ion implantation areas comprises forming at least one standard pattern consisting of a first area and a second area for use in measuring resistance, implanting first and second conduction type impurity ions into the first and second areas, respectively, and measuring a resistance of the standard pattern. The method also includes forming a misalignment inspection pattern consisting of a first area and a second area on a predetermined area within a semiconductor substrate, implanting first and second conduction type impurity ions into the misalignment inspection pattern and active regions on the semiconductor substrate, respectively, and measuring a resistance of the misalignment inspection pattern. The method concludes by comparing the resistance of the standard pattern with the resistance of the misalignment inspection pattern.
摘要翻译：检测离子注入区域的未对准的方法包括形成由用于测量电阻的第一区域和第二区域组成的至少一个标准图案，分别将第一和第二导电型杂质离子注入第一和第二区域，并测量标准模式的阻力。该方法还包括在半导体衬底内的预定区域上形成由第一区域和第二区域组成的未对准检查图案，分别将第一和第二导电型杂质离子注入到半对准检查图案和半导体衬底上的有源区域中，并测量不对准检查图案的电阻。该方法通过将标准图案的电阻与不对准检查图案的电阻进行比较来得出结论。

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