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1. 发明申请

US20120239874A1 METHOD AND SYSTEM FOR RESOLVING INTEROPERABILITY OF MULTIPLE TYPES OF DUAL IN-LINE MEMORY MODULES 审中-公开
标题翻译：用于解决多种类型的在线存储器模块的互操作性的方法和系统
公开(公告)号：US20120239874A1
公开(公告)日：2012-09-20
申请号：US13411344
申请日：2012-03-02
申请人： Hyun Lee , Jayesh R. Bhakta , Paresh Sheth
发明人： Hyun Lee , Jayesh R. Bhakta , Paresh Sheth
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F13/1673
摘要： Systems and methods are described for resolving certain interoperability issues among multiple types of memory modules in the same memory subsystem. The system provides a single data load DIMM for constructing a high density and high speed memory subsystem that supports the standard JEDEC RDIMM interface while presenting a single load to the memory controller. At least one memory module includes one or more DRAM, a bi-directional data buffer and an interface bridge with a conflict resolution block. The interface bridge translates the CAS latency (CL) programming value that a memory controller sends to program the DRAMs, modifies the latency value, and is used for resolving command conflicts between the DRAMs and the memory controller to insure proper operation of the memory subsystem.
摘要翻译：描述了系统和方法，用于解决同一内存子系统中多种类型的内存模块之间的某些互操作性问题。该系统提供单个数据加载DIMM，用于构建高密度和高速存储器子系统，支持标准JEDEC RDIMM接口，同时向存储器控制器提供单个负载。至少一个存储器模块包括一个或多个DRAM，双向数据缓冲器和具有冲突解决块的接口桥。接口桥转换存储器控制器向DRAM编程的CAS延迟（CL）编程值，修改延迟值，并用于解决DRAM和存储器控制器之间的命令冲突，以确保存储器子系统的正确操作。

2. 发明授权

US08264903B1 Systems and methods for refreshing a memory module 有权
标题翻译：用于刷新内存模块的系统和方法
公开(公告)号：US08264903B1
公开(公告)日：2012-09-11
申请号：US12774632
申请日：2010-05-05
申请人： Hyun Lee , Jayesh R. Bhakta
发明人： Hyun Lee , Jayesh R. Bhakta
IPC分类号： G11C7/00
CPC分类号： G11C11/40618 , G11C5/04 , G11C11/40611
摘要： A memory module according to certain aspects has a plurality of memory devices arranged into one or more logical ranks. Each logical rank may correspond to a set of at least two physical ranks. The memory module can include a circuit operatively coupled to the plurality of memory devices and configured to be operatively coupled to a memory controller of a computer system to receive a logical rank refresh command. In response, the circuit can initiate a first refresh operation for one or more first physical ranks and then initiate a second refresh operation for one or more second physical ranks. The memory module can further include a memory location storing a refresh time (tRFC) value accessible by the memory controller and based at least in part on a calculated maximum amount of time for refreshing the logical rank.
摘要翻译：根据某些方面的存储器模块具有布置成一个或多个逻辑等级的多个存储器件。每个逻辑等级可以对应于一组至少两个物理等级。存储器模块可以包括可操作地耦合到多个存储器件并且被配置为可操作地耦合到计算机系统的存储器控制器以接收逻辑秩刷新命令的电路。作为响应，电路可以针对一个或多个第一物理等级启动第一刷新操作，然后针对一个或多个第二物理等级启动第二刷新操作。存储器模块还可以包括存储位置，存储由存储器控制器可访问的刷新时间（tRFC）值，并至少部分地基于所计算的用于刷新逻辑等级的最大时间量。

3. 发明授权

US08782350B2 Circuit providing load isolation and noise reduction 有权
标题翻译：电路提供负载隔离和降噪
公开(公告)号：US08782350B2
公开(公告)日：2014-07-15
申请号：US13412243
申请日：2012-03-05
申请人： Hyun Lee , Jayesh R. Bhakta , Jeffrey C. Solomon , Mario Jesus Martinez , Chi-She Chen
发明人： Hyun Lee , Jayesh R. Bhakta , Jeffrey C. Solomon , Mario Jesus Martinez , Chi-She Chen
IPC分类号： G06F12/00 , H05K1/02
CPC分类号： G06F13/1684 , G06F13/4027 , G11C5/02 , G11C5/06 , G11C8/18 , H05K1/0216 , H05K1/0243 , H05K2201/10053 , H05K2201/10159 , H05K2201/10189
摘要： Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.
摘要翻译：本文描述的某些实施例包括具有印刷电路板的存储器模块，该印刷电路板包括被配置为可操作地耦合到计算机系统的存储器控制器的至少一个连接器。存储器模块还包括印刷电路板上的多个存储器件和包括可操作地耦合到至少一个存储器件的第一组端口的电路。电路还包括可操作地耦合到至少一个连接器的第二组端口。电路包括切换电路，其被配置为选择性地将第二组端口的一个或多个端口耦合到第一组端口的一个或多个端口。第一组和第二组的每个端口包括校正电路，其减少在第一组端口和第二组端口之间传输的一个或多个信号中的噪声。

4. 发明授权

US08359501B1 Memory board with self-testing capability 有权
标题翻译：内存板具有自检功能
公开(公告)号：US08359501B1
公开(公告)日：2013-01-22
申请号：US13183253
申请日：2011-07-14
申请人： Hyun Lee , Jayesh R. Bhakta , Soonju Choi
发明人： Hyun Lee , Jayesh R. Bhakta , Soonju Choi
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C5/04
摘要： A self-testing memory module includes a printed circuit board configured to be operatively coupled to a memory controller of a computer system and includes a plurality of memory devices on the printed circuit board, each memory device of the plurality of memory devices comprising data, address, and control ports. The memory module also includes a control module configured to generate address and control signals for testing the memory devices. The memory module includes a data module comprising a plurality of data handlers. Each data handler is operable independently from each of the other data handlers of the plurality of data handlers. Each data handler is operatively coupled to a corresponding plurality of the data ports of one or more of the memory devices and is configured to generate data for writing to the corresponding plurality of data ports.
摘要翻译：自检存储器模块包括被配置为可操作地耦合到计算机系统的存储器控制器的印刷电路板，并且在印刷电路板上包括多个存储器件，多个存储器件中的每个存储器件包括数据，地址和控制端口。存储器模块还包括被配置为产生用于测试存储器件的地址和控制信号的控制模块。存储器模块包括包括多个数据处理器的数据模块。每个数据处理程序可独立于多个数据处理程序中的每个其他数据处理程序操作。每个数据处理器可操作地耦合到一个或多个存储器件的对应的多个数据端口，并且被配置为产生用于写入对应的多个数据端口的数据。

5. 发明授权

US08001434B1 Memory board with self-testing capability 有权
标题翻译：内存板具有自检功能
公开(公告)号：US08001434B1
公开(公告)日：2011-08-16
申请号：US12422925
申请日：2009-04-13
申请人： Hyun Lee , Jayesh R. Bhakta , Soonju Choi
发明人： Hyun Lee , Jayesh R. Bhakta , Soonju Choi
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G11C29/12 , G11C5/04
摘要： A self-testing memory module includes a printed circuit board configured to be operatively coupled to a memory controller of a computer system and includes a plurality of memory devices on the printed circuit board, each memory device of the plurality of memory devices comprising data, address, and control ports. The memory module also includes a control module configured to generate address and control signals for testing the memory devices. The memory module includes a data module comprising a plurality of data handlers. Each data handler is operable independently from each of the other data handlers of the plurality of data handlers. Each data handler is operatively coupled to a corresponding plurality of the data ports of one or more of the memory devices and is configured to generate data for writing to the corresponding plurality of data ports.
摘要翻译：自检存储器模块包括被配置为可操作地耦合到计算机系统的存储器控制器的印刷电路板，并且在印刷电路板上包括多个存储器件，多个存储器件中的每个存储器件包括数据，地址和控制端口。存储器模块还包括被配置为产生用于测试存储器件的地址和控制信号的控制模块。存储器模块包括包括多个数据处理器的数据模块。每个数据处理程序可独立于多个数据处理程序中的每个其他数据处理程序操作。每个数据处理器可操作地耦合到一个或多个存储器件的对应的多个数据端口，并且被配置为产生用于写入对应的多个数据端口的数据。

6. 发明授权

US08417870B2 System and method of increasing addressable memory space on a memory board 有权
标题翻译：在存储器板上增加可寻址存储空间的系统和方法
公开(公告)号：US08417870B2
公开(公告)日：2013-04-09
申请号：US12504131
申请日：2009-07-16
申请人： Hyun Lee , Jayesh R. Bhakta
发明人： Hyun Lee , Jayesh R. Bhakta
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C5/04 , G06F12/0623
摘要： A load-reducing memory module includes a plurality of memory components such as DRAMs. The memory components are organized into sets or ranks such that they can be accessed simultaneously for the full data bit-width of the memory module. A plurality of load reducing switching circuits is used to drive data bits from a memory controller to the plurality of memory components. The load reducing switching circuits are also used to multiplex the data lines from the memory components and drive the data bits to the memory controller.
摘要翻译：减载存储器模块包括诸如DRAM的多个存储器组件。存储器组件被组织成集合或等级，使得它们可以被同时访问用于存储器模块的完整数据位宽。多个负载降低开关电路用于将数据位从存储器控制器驱动到多个存储器组件。负载降低开关电路还用于将来自存储器组件的数据线多路复用并将数据位驱动到存储器控制器。

7. 发明申请

US20110016269A1 SYSTEM AND METHOD OF INCREASING ADDRESSABLE MEMORY SPACE ON A MEMORY BOARD 有权
标题翻译：在存储板上增加可寻址存储空间的系统和方法
公开(公告)号：US20110016269A1
公开(公告)日：2011-01-20
申请号：US12504131
申请日：2009-07-16
申请人： Hyun Lee , Jayesh R. Bhakta
发明人： Hyun Lee , Jayesh R. Bhakta
IPC分类号： G06F12/00
CPC分类号： G11C5/04 , G06F12/0623
摘要： A load-reducing memory module includes a plurality of memory components such as DRAMs. The memory components are organized into sets or ranks such that they can be accessed simultaneously for the full data bit-width of the memory module. A plurality of load reducing switching circuits is used to drive data bits from a memory controller to the plurality of memory components. The load reducing switching circuits are also used to multiplex the data lines from the memory components and drive the data bits to the memory controller.
摘要翻译：减载存储器模块包括诸如DRAM的多个存储器组件。存储器组件被组织成集合或等级，使得它们可以被同时访问用于存储器模块的完整数据位宽。多个负载降低开关电路用于将数据位从存储器控制器驱动到多个存储器组件。负载降低开关电路还用于将来自存储器组件的数据线多路复用并将数据位驱动到存储器控制器。

8. 发明申请

US20110016250A1 SYSTEM AND METHOD UTILIZING DISTRIBUTED BYTE-WISE BUFFERS ON A MEMORY MODULE 有权
标题翻译：在存储器模块中使用分布式BY-WISE缓冲器的系统和方法
公开(公告)号：US20110016250A1
公开(公告)日：2011-01-20
申请号：US12761179
申请日：2010-04-15
申请人： Hyun Lee , Jayesh R. Bhakta
发明人： Hyun Lee , Jayesh R. Bhakta
IPC分类号： G06F13/28 , G06F12/00 , G06F13/40
CPC分类号： G06F12/00 , G11C5/025 , G11C5/04 , G11C5/066 , G11C8/12
摘要： A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.
摘要翻译：提供了利用一个或多个存储器模块的存储器系统和方法。存储器模块包括多个存储器件和被配置为从系统存储器控制器接收控制信息并产生模块控制信号的控制器。存储器模块还包括多个电路，例如逐字节缓冲器，其配置为将多个存储器设备与系统存储器控制器选择性地隔离。响应于模块控制信号，这些电路可操作地将写数据从系统存储器控制器驱动到多个存储器装置，并将来自多个存储器件的读取数据合并到系统存储器控制器。电路分布在彼此分开的相应位置。

9. 发明授权

US08516185B2 System and method utilizing distributed byte-wise buffers on a memory module 有权
标题翻译：在存储器模块上使用分布式逐字节缓冲器的系统和方法
公开(公告)号：US08516185B2
公开(公告)日：2013-08-20
申请号：US12761179
申请日：2010-04-15
申请人： Hyun Lee , Jayesh R. Bhakta
发明人： Hyun Lee , Jayesh R. Bhakta
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G11C5/025 , G11C5/04 , G11C5/066 , G11C8/12
摘要： A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.
摘要翻译：提供了利用一个或多个存储器模块的存储器系统和方法。存储器模块包括多个存储器件和被配置为从系统存储器控制器接收控制信息并产生模块控制信号的控制器。存储器模块还包括多个电路，例如逐字节缓冲器，其配置为将多个存储器设备与系统存储器控制器选择性地隔离。响应于模块控制信号，这些电路可操作地将写数据从系统存储器控制器驱动到多个存储器装置，并将来自多个存储器件的读取数据合并到系统存储器控制器。电路分布在彼此分开的相应位置。

10. 发明申请

US20120250386A1 CIRCUIT PROVIDING LOAD ISOLATION AND NOISE REDUCTION 有权
标题翻译：电路提供负载分离和噪声减少
公开(公告)号：US20120250386A1
公开(公告)日：2012-10-04
申请号：US13412243
申请日：2012-03-05
申请人： Hyun Lee , Jayesh R. Bhakta , Jeffrey C. Solomon , Mario Jesus Martinez , Chi-She Chen
发明人： Hyun Lee , Jayesh R. Bhakta , Jeffrey C. Solomon , Mario Jesus Martinez , Chi-She Chen
IPC分类号： G11C5/02
CPC分类号： G06F13/1684 , G06F13/4027 , G11C5/02 , G11C5/06 , G11C8/18 , H05K1/0216 , H05K1/0243 , H05K2201/10053 , H05K2201/10159 , H05K2201/10189
摘要： Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.
摘要翻译：本文描述的某些实施例包括具有印刷电路板的存储器模块，该印刷电路板包括被配置为可操作地耦合到计算机系统的存储器控制器的至少一个连接器。存储器模块还包括印刷电路板上的多个存储器件和包括可操作地耦合到至少一个存储器件的第一组端口的电路。电路还包括可操作地耦合到至少一个连接器的第二组端口。电路包括切换电路，其被配置为选择性地将第二组端口的一个或多个端口耦合到第一组端口的一个或多个端口。第一组和第二组的每个端口包括校正电路，其减少在第一组端口和第二组端口之间传输的一个或多个信号中的噪声。

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