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    • 1. 发明授权
    • Clock gated bus keeper
    • 时钟门控巴士管家
    • US06484267B1
    • 2002-11-19
    • US09474413
    • 1999-12-29
    • Hyun LeeDavid W. Potter
    • Hyun LeeDavid W. Potter
    • G06F104
    • G06F13/4077
    • The present invention comprises a clocked bus keeper circuit that does not drive the bus during the first half of a clock cycle and then holds the value driven onto the bus during the first half of the clock cycle for the second half of the clock cycle. Accordingly, true data drivers on the bus drive the bus during the first half of the clock cycle without the need to overcome the value driven by the bus keeper, but during the second half of the clock cycle, the bus keeper holds the data driven during the first half of the clock cycle. In this manner, there is no bus contention between the true bus data drivers and the bus keeper.
    • 本发明包括时钟总线保持器电路,其在时钟周期的前半部分期间不驱动总线,然后在时钟周期的后半部分的时钟周期的前半部分期间保持被驱动到总线上的值。 因此,总线上的真实数据驱动器在时钟周期的前半部分驱动总线,而不需要克服由总线管理器驱动的值,但是在时钟周期的后半段,总线管理器保持在 时钟周期的前半部分。 以这种方式,真正的总线数据驱动器和总线管理器之间没有总线争用。
    • 2. 发明授权
    • Method and apparatus for using a bus as a data storage node
    • 一种使用总线作为数据存储节点的方法和装置
    • US06725305B1
    • 2004-04-20
    • US09474412
    • 1999-12-29
    • Hyun LeeDavid W. PotterLai Q. Pham
    • Hyun LeeDavid W. PotterLai Q. Pham
    • G06F1300
    • G06F13/4077
    • The present invention is a method and apparatus for dynamically holding valid data logic levels on a bus by taking advantage of the inherent storage capacity of the bus. The bus speed is increased by eliminating the use of active bus keepers and null cycles. Instead, a two phase clock is used, the bus drivers drive data onto the bus during the first phase of the clock and are turned off at the beginning of the second phase of the bus clock. The receiving device latches the data during the second phase of the bus clock. Accordingly, there is no need for a null cycle or a bus keeper circuit, yet there is no bus contention between consecutive drivers nor is there a floating node condition.
    • 本发明是一种通过利用总线的固有存储容量来在总线上动态地保持有效数据逻辑电平的方法和装置。 通过消除使用有效的总线管理器和空循环来增加总线速度。 相反,使用两相时钟,总线驱动器在时钟的第一阶段将数据驱动到总线上,并且在总线时钟的第二阶段开始时被关断。 接收装置在总线时钟的第二阶段期间锁存数据。 因此,不需要空循环或总线保护电路,但是在连续驱动器之间没有总线争用,也没有浮动节点条件。
    • 3. 发明授权
    • Data bus method and apparatus providing variable data rates using a smart bus arbiter
    • 使用智能总线仲裁器提供可变数据速率的数据总线方法和装置
    • US06611893B1
    • 2003-08-26
    • US09474411
    • 1999-12-29
    • Hyun LeeDavid W. Potter
    • Hyun LeeDavid W. Potter
    • G06F1336
    • G06F13/364
    • A method and apparatus for arbitrating access to a bus such that the bus can operate at a variable data rate, that rate being the rate of the slower of the two devices communicating over the bus. The smart arbiter in accordance with the invention has knowledge of the speed of the devices that use the bus and grants access in an order and at a rate based on that information. The smart arbiter can intersperse grants such that data transfers between multiple pairs of transmitting and receiving devices that are not independently utilizing the maximum bandwidth capabilities of the bus can overlap. Thus, if one pair of devices are exchanging multiple consecutive words (or other units of data) at a rate slower than the maximum rate of the bus, another pair of devices can use some of the bus clock cycles between the transfer of words of the first device pair, for transfers of words between the second device pair.
    • 用于仲裁对总线的访问的方法和装置,使得总线可以以可变数据速率操作,该速率是两个设备在总线上通信的速度较慢的速率。 根据本发明的智能仲裁器知道使用总线的设备的速度,并且以订​​单和基于该信息的速率授予访问权。 智能仲裁器可以散布授权,使得不是独立地利用总线的最大带宽能力的多对发送和接收设备之间的数据传输可以重叠。 因此,如果一对设备以比总线的最大速率慢的速率交换多个连续字(或其他数据单元),则另一对设备可以使用一些总线时钟周期来传送 第一设备对,用于在第二设备对之间传送字。