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1. 发明申请

US20100267225A1 Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20100267225A1
公开(公告)日：2010-10-21
申请号：US12385658
申请日：2009-04-15
申请人： Hyo-san Lee , Bo-un Yoon , Kun-tack Lee , Dae-hyuk Kang , Jeong-nam Han , Jung-jae Myung , Hyung-pyo Hong , Hun-pyo Hong
发明人： Hyo-san Lee , Bo-un Yoon , Kun-tack Lee , Dae-hyuk Kang , Jeong-nam Han , Jung-jae Myung , Hyung-pyo Hong , Hun-pyo Hong
IPC分类号： H01L21/265 , H01L21/306
CPC分类号： H01L21/31133 , G03F7/423 , H01L21/0206 , H01L21/02071
摘要： A method of manufacturing a semiconductor device, the method including forming a photoresist film on a substrate, and removing the photoresist film from the substrate using a composition that includes a sulfuric acid solution, a hydrogen peroxide solution, and a corrosion inhibitor.
摘要翻译：一种制造半导体器件的方法，所述方法包括在衬底上形成光致抗蚀剂膜，并且使用包含硫酸溶液，过氧化氢溶液和腐蚀抑制剂的组合物从衬底去除光致抗蚀剂膜。

2. 发明授权

US06610596B1 Method of forming metal interconnection using plating and semiconductor device manufactured by the method 有权
标题翻译：使用该方法制造的使用电镀和半导体器件形成金属互连的方法
公开(公告)号：US06610596B1
公开(公告)日：2003-08-26
申请号：US09662120
申请日：2000-09-14
申请人： Jong-won Lee , Bo-un Yoon , Kun-tack Lee , Sang-rok Hah
发明人： Jong-won Lee , Bo-un Yoon , Kun-tack Lee , Sang-rok Hah
IPC分类号： H01L2144
CPC分类号： H01L21/7684 , H01L21/76879
摘要： A method is provided for forming a metal interconnection using a plating process, which can improve the throughput and reliability of semiconductor devices by decreasing the required polishing in a chemical mechanical polishing process. A semiconductor device manufactured by this method is also provided. In the method of forming a metal interconnection, a recess region is formed in a portion of an insulation layer formed over a substrate, i.e., where a metal interconnection layer will be formed. A diffusion prevention layer is formed over the substrate, the insulation layer, and the recess region. Then, a metal seed layer is formed over the diffusion prevention layer only in the recess region using a chemical mechanical polishing process or an etch back process. A conductive plating layer is then formed on the metal seed layer only in the recess region. Thereafter, surface polarization is performed to form a metal interconnection layer in the recess region. The plating layer may be formed after forming the seed layer only in the bottom portion of the recess region.
摘要翻译：提供了一种使用电镀工艺形成金属互连的方法，其可以通过减少化学机械抛光工艺中所需的抛光来提高半导体器件的生产能力和可靠性。还提供了通过该方法制造的半导体器件。在形成金属互连的方法中，在形成在基板上的绝缘层的一部分中，即将形成金属互连层的区域中形成凹陷区域。在基板，绝缘层和凹部区域上形成扩散防止层。然后，使用化学机械抛光工艺或回蚀工艺，仅在凹陷区域中在扩散防止层上形成金属种子层。然后在金属种子层上仅在凹陷区域中形成导电镀层。此后，进行表面极化以在凹部区域中形成金属互连层。可以在仅在凹部的底部形成种子层之后形成镀层。

3. 发明授权

US09728535B2 Methods of fabricating semiconductor devices including fin-shaped active regions 有权
公开(公告)号：US09728535B2
公开(公告)日：2017-08-08
申请号：US15058664
申请日：2016-03-02
申请人： Young-sang Youn , Myung-geun Song , Ji-hoon Cha , Jae-jik Baek , Bo-un Yoon , Jeong-nam Han
发明人： Young-sang Youn , Myung-geun Song , Ji-hoon Cha , Jae-jik Baek , Bo-un Yoon , Jeong-nam Han
IPC分类号： H01L21/76 , H01L27/088 , H01L21/762 , H01L21/8234 , H01L21/84 , H01L29/06
CPC分类号： H01L21/76229 , H01L21/2652 , H01L21/763 , H01L21/823431 , H01L21/823481 , H01L21/845 , H01L27/0886 , H01L29/0649 , H01L29/0657
摘要： A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.

4. 发明申请

US20160181243A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING FIN-SHAPED ACTIVE REGIONS 审中-公开
标题翻译：制造精细形状活性区域的半导体器件的方法
公开(公告)号：US20160181243A1
公开(公告)日：2016-06-23
申请号：US15058664
申请日：2016-03-02
申请人： Young-sang Youn , Myung-geun Song , Ji-hoon Cha , Jae-jik Baek , Bo-un Yoon , Jeong-nam Han
发明人： Young-sang Youn , Myung-geun Song , Ji-hoon Cha , Jae-jik Baek , Bo-un Yoon , Jeong-nam Han
IPC分类号： H01L27/088 , H01L29/06
CPC分类号： H01L21/76229 , H01L21/2652 , H01L21/763 , H01L21/823431 , H01L21/823481 , H01L21/845 , H01L27/0886 , H01L29/0649 , H01L29/0657
摘要： A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
摘要翻译：一种制造半导体器件的方法包括：通过在衬底中形成以第一间距重复的多个第一器件隔离沟槽来形成多个鳍片，形成从第一器件隔离的顶表面突出的多个翅片型有源区域通过在所述多个第一器件隔离沟槽中形成所述第一器件隔离层，通过蚀刻所述衬底和所述第一器件隔离层的一部分来形成以与所述第一间距不同的间距隔离沟槽的多个第二器件，在所述多个第二器件隔离沟槽中的第二器件隔离层，以便形成彼此分离的多个鳍式有源区域组，其间具有第二器件隔离层。

5. 发明授权

US08030150B2 Method of fabricating non-volatile memory integrated circuit device and non-volatile memory integrated circuit device fabricated using the same 有权
标题翻译：制造非易失性存储器集成电路器件的方法和使用其制造的非易失性存储器集成电路器件
公开(公告)号：US08030150B2
公开(公告)日：2011-10-04
申请号：US12397543
申请日：2009-03-04
申请人： Byoung-ho Kwon , Chang-ki Hong , Bo-un Yoon , Jun-yong Kim
发明人： Byoung-ho Kwon , Chang-ki Hong , Bo-un Yoon , Jun-yong Kim
IPC分类号： H01L21/8238
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.
摘要翻译：提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。结区域形成在单元阵列区域中。间隔件形成在第一和第二预堆叠栅极结构的侧壁上。形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。去除第二牺牲层图案。在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

6. 发明申请

US20100062548A1 PHOTO KEY AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE PHOTO KEY 有权
标题翻译：使用照相钥匙制作半导体器件的照相钥匙和方法
公开(公告)号：US20100062548A1
公开(公告)日：2010-03-11
申请号：US12475713
申请日：2009-06-01
申请人： Byoung-ho Kwon , Chang-ki Hong , Bo-un Yoon , Jae-dong Lee , Sang-jin Kim
发明人： Byoung-ho Kwon , Chang-ki Hong , Bo-un Yoon , Jae-dong Lee , Sang-jin Kim
IPC分类号： H01L21/66 , H01L23/544
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.
摘要翻译：光钥匙具有在半导体衬底上彼此间隔开的多个第一区域和围绕第一区域的第二区域，并且第一区域和第二区域中的一个构成彼此间隔开的多个光键区域。每个照片键区域包括彼此间隔开的多个第一导电图案; 以及介于所述第一导电图案之间的多个第二导电图案。

7. 发明申请

US20080017915A1 Method of Fabricating Non-Volatile Memory Integrated Circuit Device and Non-Volatile Memory Integrated Circuit Device Fabricated Using the Same 有权
标题翻译：制造非易失性存储器集成电路器件和使用其的非易失性存储器集成电路器件的方法
公开(公告)号：US20080017915A1
公开(公告)日：2008-01-24
申请号：US11763137
申请日：2007-06-14
申请人： Byoung-ho KWON , Chang-ki Hong , Bo-un Yoon , Jun-yong Kim
发明人： Byoung-ho KWON , Chang-ki Hong , Bo-un Yoon , Jun-yong Kim
IPC分类号： H01L27/105 , H01L21/8229
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.
摘要翻译：提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。结区域形成在单元阵列区域中。间隔件形成在第一和第二预堆叠栅极结构的侧壁上。形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。去除第二牺牲层图案。在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

8. 发明申请

US20070155178A1 Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same 审中-公开
标题翻译：用于化学机械抛光工艺的浆料及使用其制造半导体器件的方法
公开(公告)号：US20070155178A1
公开(公告)日：2007-07-05
申请号：US11712931
申请日：2007-03-01
申请人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phill Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
发明人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phill Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
IPC分类号： H01L21/306 , H01L21/461 , B44C1/22 , C23F1/00 , H01L21/302
CPC分类号： H01L21/76224 , B24B37/044 , C09G1/02 , H01L21/31053
摘要： A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.
摘要翻译：公开了一种用于材料层表面例如氧化硅层的化学机械抛光的浆料组合物。暴露于浆料的第一材料表面显示出亲水性，而第二材料层，例如其表面也暴露于浆料的多晶硅层，表现出疏水性，因此用作抛光停止层。浆料组合物基本上由水，磨料颗粒和具有亲水和疏水官能团的聚合物添加剂组成。

9. 发明申请

US20140220752A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140220752A1
公开(公告)日：2014-08-07
申请号：US13799291
申请日：2013-03-13
申请人： Jae-Young PARK , Ji-Hoon Cha , Jae-Jik Baek , Bon-Young Koo , Kang-Hun Moon , Bo-un Yoon
发明人： Jae-Young PARK , Ji-Hoon Cha , Jae-Jik Baek , Bon-Young Koo , Kang-Hun Moon , Bo-un Yoon
IPC分类号： H01L29/66
CPC分类号： H01L29/66795
摘要： A method of fabricating a semiconductor device is described. The method of fabricating a semiconductor device comprises providing a fin formed to protrude from a substrate and a plurality of gate electrodes formed on the fin to intersect the fin; forming first recesses in the fin on at least one side of the respective gate electrodes; forming an oxide layer on the surfaces of the first recesses; and expanding the first recesses into second recesses by removing the oxide layer. Related devices are also disclosed.
摘要翻译：描述制造半导体器件的方法。制造半导体器件的方法包括提供形成为从基板突出的翅片和形成在鳍片上的与栅极相交的多个栅电极; 在所述翅片的至少一个侧面上形成第一凹部; 在所述第一凹部的表面上形成氧化物层; 并且通过去除氧化物层将第一凹槽膨胀成第二凹陷。还公开了相关设备。

10. 发明申请

US20110294285A1 PHOTO KEY AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE PHOTO KEY 有权
标题翻译：使用照相钥匙制作半导体器件的照相钥匙和方法
公开(公告)号：US20110294285A1
公开(公告)日：2011-12-01
申请号：US13204752
申请日：2011-08-08
申请人： Byoung-ho Kwon , Chang-ki Hong , Bo-un Yoon , Jae-dong Lee , Sang-jin Kim
发明人： Byoung-ho Kwon , Chang-ki Hong , Bo-un Yoon , Jae-dong Lee , Sang-jin Kim
IPC分类号： H01L21/28
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.
摘要翻译：光钥匙具有在半导体衬底上彼此间隔开的多个第一区域和围绕第一区域的第二区域，并且第一区域和第二区域中的一个构成彼此间隔开的多个光键区域。每个照片键区域包括彼此间隔开的多个第一导电图案; 以及介于所述第一导电图案之间的多个第二导电图案。

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