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1. 发明申请

US20060049439A1 Image device and method of fabricating the same 审中-公开
标题翻译：图像装置及其制造方法
公开(公告)号：US20060049439A1
公开(公告)日：2006-03-09
申请号：US11220295
申请日：2005-09-06
申请人： Hyeok-Sang Oh , Ju-Hyuck Chung , Kwang-Myeon Park , In-Soo Cho , Seong-Il Kim
发明人： Hyeok-Sang Oh , Ju-Hyuck Chung , Kwang-Myeon Park , In-Soo Cho , Seong-Il Kim
IPC分类号： H01L31/062
CPC分类号： H01L27/14625 , H01L27/14609 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14643 , H01L27/14685 , H01L27/14687
摘要： An image device includes a substrate in which a light receiving element is formed, an interlayer dielectric structure which is formed on the substrate and has a cavity over the light receiving element, a transparent dielectric layer which fills the cavity and has a lens-shaped portion protruding beyond an upper portion of the interlayer dielectric structure, and a color filter which is formed on the transparent dielectric layer.
摘要翻译：图像装置包括其中形成有光接收元件的基板，形成在基板上并且在光接收元件上方具有空腔的层间电介质结构，填充空腔并具有透镜形状部分的透明电介质层突出超过层间电介质结构的上部，以及形成在透明电介质层上的滤色器。

2. 发明授权

US08232200B1 Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby 有权
标题翻译：形成具有金属扩散阻挡层和由此形成的器件的具有镶嵌互连的集成电路器件的方法
公开(公告)号：US08232200B1
公开(公告)日：2012-07-31
申请号：US13051732
申请日：2011-03-18
申请人： Hyeok-Sang Oh , Woo-Jin Jang , Bum-Ki Moon , Ji-Hong Choi , Minseok Oh , Tien-Jen Cheng
发明人： Hyeok-Sang Oh , Woo-Jin Jang , Bum-Ki Moon , Ji-Hong Choi , Minseok Oh , Tien-Jen Cheng
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76885
摘要： Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.
摘要翻译：形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。层间绝缘层的上表面被凹入以暴露电互连的侧壁。电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。该金属扩散阻挡层可以使用化学镀技术形成。

3. 发明授权

US08373273B2 Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby 有权
标题翻译：形成具有金属扩散阻挡层和由此形成的器件的具有镶嵌互连的集成电路器件的方法
公开(公告)号：US08373273B2
公开(公告)日：2013-02-12
申请号：US13533135
申请日：2012-06-26
申请人： Hyeok-Sang Oh , Woo-Jin Jang , Bum-Ki Moon , Ji-Hong Choi , Minseok Oh , Tien-Jen Cheng
发明人： Hyeok-Sang Oh , Woo-Jin Jang , Bum-Ki Moon , Ji-Hong Choi , Minseok Oh , Tien-Jen Cheng
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76844 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76885
摘要： Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.
摘要翻译：形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。层间绝缘层的上表面被凹入以暴露电互连的侧壁。电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。该金属扩散阻挡层可以使用化学镀技术形成。

4. 发明申请

US20120267785A1 METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING DAMASCENE INTERCONNECTS THEREIN WITH METAL DIFFUSION BARRIER LAYERS AND DEVICES FORMED THEREBY 有权
标题翻译：形成集成电路装置的方法，其具有金属扩散阻挡层和形成的器件的大分子互连
公开(公告)号：US20120267785A1
公开(公告)日：2012-10-25
申请号：US13533135
申请日：2012-06-26
申请人： Hyeok-Sang Oh , Woo-Jin Jang , Bum-Ki Moon , Ji-Hong Choi , Minseok Oh , Tien-Jen Cheng
发明人： Hyeok-Sang Oh , Woo-Jin Jang , Bum-Ki Moon , Ji-Hong Choi , Minseok Oh , Tien-Jen Cheng
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/76844 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76885
摘要： Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.
摘要翻译：形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。层间绝缘层的上表面被凹入以暴露电互连的侧壁。电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。该金属扩散阻挡层可以使用化学镀技术形成。

5. 发明申请

US20100038793A1 INTERCONNECT STRUCTURES COMPRISING CAPPING LAYERS WITH LOW DIELECTRIC CONSTANTS AND METHODS OF MAKING THE SAME 失效
标题翻译：包含具有低介电常数的封装层的互连结构及其制造方法
公开(公告)号：US20100038793A1
公开(公告)日：2010-02-18
申请号：US12190131
申请日：2008-08-12
申请人： Griselda Bonilla , Tien Cheng , Lawrence A. Clevenger , Stephan Grunow , Chao-Kun Hu , Roger A. Quon , Zhiguo Sun , Wei-tsui Tseng , Yiheng Xu , Yun Wang , Hyeok-Sang Oh
发明人： Griselda Bonilla , Tien Cheng , Lawrence A. Clevenger , Stephan Grunow , Chao-Kun Hu , Roger A. Quon , Zhiguo Sun , Wei-tsui Tseng , Yiheng Xu , Yun Wang , Hyeok-Sang Oh
IPC分类号： H01L23/48
CPC分类号： H01L21/76834 , H01L21/76826 , H01L21/76832 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiwCxNyHz disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiwCxNyHz disposed upon the second capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.
摘要翻译：提供包括具有低介电常数和良好氧阻隔性能的封盖层的互连结构及其制备方法。在一个实施例中，集成电路结构包括：设置在半导体衬底之上的层间电介质层; 嵌入在所述层间电介质层中的导电互连; 包括设置在所述导电互连上的SiwCxNyHz的第一覆盖层; 包含设置在第一覆盖层上的介电常数小于约4的SiaCbNcHd（具有较小N）的第二覆盖层; 以及第三覆盖层，其包括设置在所述第二覆盖层上的SiwCxNyHz，其中a + b + c + d = 1.0和a，b，c和d各自大于0且小于1，并且其中w + x + y + z = 1.0，w，x，y和z分别大于0且小于1。

6. 发明授权

US07163890B2 Methods of fabricating semiconductor device having slope at lower sides of interconnection hole with etch-stop layer 有权
标题翻译：制造具有蚀刻停止层的互连孔下侧具有斜面的半导体器件的方法
公开(公告)号：US07163890B2
公开(公告)日：2007-01-16
申请号：US10910922
申请日：2004-08-04
申请人： Ki-Ho Kang , Hyeok-Sang Oh , Jung-Woo Lee , Dae-Keun Park
发明人： Ki-Ho Kang , Hyeok-Sang Oh , Jung-Woo Lee , Dae-Keun Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76804 , H01L21/76807 , H01L21/76834 , H01L21/76835
摘要： Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step is formed in the etch-stop layer by removing portions of the exposed etch-stop layer. And, the step is formed at a boundary between a recessed portion of the exposed etch-stop layer and a raised portion of the etch-stop layer covered with the interlayer dielectric layer. Portions of the interlayer dielectric layer are removed to expose portions of the raised portion of the etch-stop layer. And, the exposed recessed and raised portions are anisotropically etched to expose the lower conductive layer and to form the interconnection hole having the slopes, wherein the slopes are made of a residual etch-stop layer at the lower sides of the interconnection hole.
摘要翻译：制造在互连孔的下侧具有斜面的半导体器件的方法包括依次形成在具有下导电层的半导体衬底上的蚀刻停止层和层间电介质层。蚀刻停止层的一部分通过选择性蚀刻层间电介质层而被曝光。通过去除暴露的蚀刻停止层的部分，在蚀刻停止层中形成台阶。并且，该步骤形成在暴露的蚀刻停止层的凹陷部分和被层间介电层覆盖的蚀刻停止层的凸起部分之间的边界处。去除层间绝缘层的一部分以暴露蚀刻停止层的凸起部分的部分。并且，各向异性蚀刻暴露的凹部和凸起部分以暴露下导电层并形成具有斜面的互连孔，其中斜面由互连孔的下侧的残留蚀刻停止层制成。

7. 发明授权

US10229876B2 Wiring structures and semiconductor devices 有权
公开(公告)号：US10229876B2
公开(公告)日：2019-03-12
申请号：US15073640
申请日：2016-03-17
申请人： Jun-Jung Kim , Young-Bae Kim , Jong-Sam Kim , Jin-Hyeung Park , Jeong-Hoon Ahn , Hyeok-Sang Oh , Kyoung-Woo Lee , Hyo-Seon Lee , Suk-Hee Jang
发明人： Jun-Jung Kim , Young-Bae Kim , Jong-Sam Kim , Jin-Hyeung Park , Jeong-Hoon Ahn , Hyeok-Sang Oh , Kyoung-Woo Lee , Hyo-Seon Lee , Suk-Hee Jang
IPC分类号： H01L23/535 , H01L23/528 , H01L23/522 , H01L27/088 , H01L23/532 , H01L21/768 , H01L21/8234 , H01L23/485
摘要： A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.

8. 发明授权

US07534720B2 Methods of fabricating semiconductor device having slope at lower sides of interconnection hole with etch-stop layer 有权
标题翻译：制造具有蚀刻停止层的互连孔下侧具有斜面的半导体器件的方法
公开(公告)号：US07534720B2
公开(公告)日：2009-05-19
申请号：US11608500
申请日：2006-12-08
申请人： Ki-Ho Kang , Hyeok-Sang Oh , Jung-Woo Lee , Dae-Keun Park
发明人： Ki-Ho Kang , Hyeok-Sang Oh , Jung-Woo Lee , Dae-Keun Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76804 , H01L21/76807 , H01L21/76834 , H01L21/76835
摘要： Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step is formed in the etch-stop layer by removing portions of the exposed etch-stop layer. And, the step is formed at a boundary between a recessed portion of the exposed etch-stop layer and a raised portion of the etch-stop layer covered with the interlayer dielectric layer. Portions of the interlayer dielectric layer are removed to expose portions of the raised portion of the etch-stop layer. And, the exposed recessed and raised portions are anisotropically etched to expose the lower conductive layer and to form the interconnection hole having the slopes, wherein the slopes are made of a residual etch-stop layer at the lower sides of the interconnection hole.
摘要翻译：制造在互连孔的下侧具有斜面的半导体器件的方法包括依次形成在具有下导电层的半导体衬底上的蚀刻停止层和层间电介质层。蚀刻停止层的一部分通过选择性蚀刻层间电介质层而被曝光。通过去除暴露的蚀刻停止层的部分，在蚀刻停止层中形成台阶。并且，该步骤形成在暴露的蚀刻停止层的凹陷部分和被层间介电层覆盖的蚀刻停止层的凸起部分之间的边界处。去除层间绝缘层的一部分以暴露蚀刻停止层的凸起部分的部分。并且，各向异性蚀刻暴露的凹部和凸起部分以暴露下导电层并形成具有斜面的互连孔，其中斜面由互连孔的下侧的残留蚀刻停止层制成。

9. 发明申请

US20070082484A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICE HAVING SLOPE AT LOWER SIDES OF INTERCONNECTION HOLE WITH ETCH-STOP LAYER 有权
标题翻译：在具有阻塞层的互连孔的下侧制作具有斜面的半导体器件的方法
公开(公告)号：US20070082484A1
公开(公告)日：2007-04-12
申请号：US11608500
申请日：2006-12-08
申请人： Ki-Ho Kang , Hyeok-Sang Oh , Jung-Woo Lee , Dae-Keun Park
发明人： Ki-Ho Kang , Hyeok-Sang Oh , Jung-Woo Lee , Dae-Keun Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76804 , H01L21/76807 , H01L21/76834 , H01L21/76835
摘要： Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step is formed in the etch-stop layer by removing portions of the exposed etch-stop layer. And, the step is formed at a boundary between a recessed portion of the exposed etch-stop layer and a raised portion of the etch-stop layer covered with the interlayer dielectric layer. Portions of the interlayer dielectric layer are removed to expose portions of the raised portion of the etch-stop layer. And, the exposed recessed and raised portions are anisotropically etched to expose the lower conductive layer and to form the interconnection hole having the slopes, wherein the slopes are made of a residual etch-stop layer at the lower sides of the interconnection hole.
摘要翻译：制造在互连孔的下侧具有斜面的半导体器件的方法包括依次形成在具有下导电层的半导体衬底上的蚀刻停止层和层间电介质层。蚀刻停止层的一部分通过选择性蚀刻层间电介质层而被曝光。通过去除暴露的蚀刻停止层的部分，在蚀刻停止层中形成台阶。并且，该步骤形成在暴露的蚀刻停止层的凹陷部分和被层间介电层覆盖的蚀刻停止层的凸起部分之间的边界处。去除层间绝缘层的一部分以暴露蚀刻停止层的凸起部分的部分。并且，各向异性蚀刻暴露的凹部和凸起部分以暴露下导电层并形成具有斜面的互连孔，其中斜面由互连孔的下侧的残留蚀刻停止层制成。

10. 发明申请

US20050054192A1 Methods of fabricating semiconductor device having slope at lower sides of interconnection hole with etch-stop layer 有权
标题翻译：制造具有蚀刻停止层的互连孔下侧具有斜面的半导体器件的方法
公开(公告)号：US20050054192A1
公开(公告)日：2005-03-10
申请号：US10910922
申请日：2004-08-04
申请人： Ki-Ho Kang , Hyeok-Sang Oh , Jung-Woo Lee , Dae-Keun Park
发明人： Ki-Ho Kang , Hyeok-Sang Oh , Jung-Woo Lee , Dae-Keun Park
IPC分类号： H01L21/28 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76808 , H01L21/76804 , H01L21/76807 , H01L21/76834 , H01L21/76835
摘要： Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step is formed in the etch-stop layer by removing portions of the exposed etch-stop layer. And, the step is formed at a boundary between a recessed portion of the exposed etch-stop layer and a raised portion of the etch-stop layer covered with the interlayer dielectric layer. Portions of the interlayer dielectric layer are removed to expose portions of the raised portion of the etch-stop layer. And, the exposed recessed and raised portions are anisotropically etched to expose the lower conductive layer and to form the interconnection hole having the slopes, wherein the slopes are made of a residual etch-stop layer at the lower sides of the interconnection hole.
摘要翻译：制造在互连孔的下侧具有斜面的半导体器件的方法包括依次形成在具有下导电层的半导体衬底上的蚀刻停止层和层间电介质层。蚀刻停止层的一部分通过选择性蚀刻层间电介质层而被曝光。通过去除暴露的蚀刻停止层的部分，在蚀刻停止层中形成台阶。并且，该步骤形成在暴露的蚀刻停止层的凹陷部分和被层间介电层覆盖的蚀刻停止层的凸起部分之间的边界处。去除层间绝缘层的一部分以暴露蚀刻停止层的凸起部分的部分。并且，各向异性蚀刻暴露的凹部和凸起部分以暴露下导电层并形成具有斜面的互连孔，其中斜面由互连孔的下侧的残留蚀刻停止层制成。

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