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1. 发明授权

US07473600B2 Nonvolatile memory device and method of forming the same 有权
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US07473600B2
公开(公告)日：2009-01-06
申请号：US11700370
申请日：2007-01-31
申请人： Hwan-Bae Yoo , Hyun-Chul Shin
发明人： Hwan-Bae Yoo , Hyun-Chul Shin
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： In a method of forming a nonvolatile memory device, and in devices formed according to the method, a hard mask used in patterning a stacked structure constituting a memory cell is simultaneously removed when a device isolation region is removed from a region of the substrate where a common source line is to be formed.
摘要翻译：在形成非易失性存储器件的方法中，并且在根据该方法形成的器件中，当从基板的区域去除器件隔离区域时，同时去除构成存储单元的层叠结构的图案形成用的硬掩模，共同源线将要形成。

2. 发明申请

US20070184616A1 Nonvolatile memory device and method of forming the same 有权
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US20070184616A1
公开(公告)日：2007-08-09
申请号：US11700370
申请日：2007-01-31
申请人： Hwan-Bae Yoo , Hyun-Chul Shin
发明人： Hwan-Bae Yoo , Hyun-Chul Shin
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： In a method of forming a nonvolatile memory device, and in devices formed according to the method, a hard mask used in patterning a stacked structure constituting a memory cell is simultaneously removed when a device isolation region is removed from a region of the substrate where a common source line is to be formed.
摘要翻译：在形成非易失性存储器件的方法中，并且在根据该方法形成的器件中，当从基板的区域去除器件隔离区域时，同时去除构成存储单元的层叠结构的图案形成用的硬掩模，共同源线将要形成。

3. 发明申请

US20060182736A1 Transducible dna-binding proteins 审中-公开
标题翻译：可转导的dna结合蛋白
公开(公告)号：US20060182736A1
公开(公告)日：2006-08-17
申请号：US10559806
申请日：2004-06-10
申请人： Jin-Soo Kim , Hyun-Chul Shin , Heung-Sun Kwon
发明人： Jin-Soo Kim , Hyun-Chul Shin , Heung-Sun Kwon
IPC分类号： A61K38/46 , C07H21/04 , C12P21/06 , C12N9/64 , A61K33/32 , C12N5/08
CPC分类号： C07K14/47 , A61K38/00 , C07K2319/81
摘要： Disclosed is a chimeric protein comprising: a) a plurality of zinc finger domains; and b) a heterologous protein transduction domain, effective for translocating the protein across a cellular membrane. The chimeric protein can be efficiently transduced into cultured eukaryotic cells in which they regulate specific target genes. Thus, artificial transcription factors that include a PTD can be used to produce protein drugs that regulate endogenous genes and protein drugs that alter cell behavior in vitro and in vivo.
摘要翻译：公开了一种嵌合蛋白质，其包含：a）多个锌指结构域; 和b）异源蛋白转导结构域，其有效地将蛋白质转移到细胞膜上。嵌合蛋白可以有效地转导到培养的真核细胞中，其中它们调节特异性靶基因。因此，包括PTD的人工转录因子可用于产生调节体内和体内改变细胞行为的内源基因和蛋白质药物的蛋白质药物。

4. 发明申请

US20060251643A1 Regulatory zinc finger proteins 审中-公开
标题翻译：调节锌指蛋白
公开(公告)号：US20060251643A1
公开(公告)日：2006-11-09
申请号：US10538041
申请日：2003-12-09
申请人： Jin-Soo Kim , Hyun-Chul Shin , Heung-Sun Kwon
发明人： Jin-Soo Kim , Hyun-Chul Shin , Heung-Sun Kwon
IPC分类号： A61K38/46 , C07H21/04 , C12P21/06 , C12N9/64
CPC分类号： C07K14/475 , C07K14/4702
摘要： Disclosed are chimeric zinc finger proteins that can regulate endogenous genes. Examples of such proteins include proteins that can regulate VEGF-A expression. The proteins and nucleic acid encoding them can be used to modulate angiogenesis.
摘要翻译：公开了可调节内源基因的嵌合锌指蛋白。这些蛋白质的实例包括可以调节VEGF-A表达的蛋白质。编码它们的蛋白质和核酸可用于调节血管发生。

5. 发明申请

US20120226865A1 NETWORK-ON-CHIP SYSTEM INCLUDING ACTIVE MEMORY PROCESSOR 审中-公开
标题翻译：包括主动内存处理器在内的网络芯片系统
公开(公告)号：US20120226865A1
公开(公告)日：2012-09-06
申请号：US13504923
申请日：2009-12-09
申请人： Ki-Young Choi , Jun-Hee Yoo , Sung-Joo Yoo , Hyun-Chul Shin
发明人： Ki-Young Choi , Jun-Hee Yoo , Sung-Joo Yoo , Hyun-Chul Shin
IPC分类号： G06F12/08
CPC分类号： G06F13/1642 , G06F2213/0038
摘要： Disclosed is a network-on-chip system including an active memory processor for processing increased communication latency by multiple processors and memories. The network-on-chip system includes a plurality of processing elements that request to perform an active memory operation for a predetermined operation from a shared memory to reduce access latency of the shared memory, and an active memory processor connected to the processing elements through a network, storing codes for processing custom transaction in request to the active memory operation, performing an operation addresses or data stored in a shared cache memory or the shared memory based on the codes and transmitting the performed operation result to the processing elements.
摘要翻译：公开了一种片上网络系统，其包括用于处理由多个处理器和存储器增加的通信延迟的主动存储器处理器。片上网络系统包括多个处理元件，其要求从共享存储器执行用于预定操作的活动存储器操作以减少共享存储器的访问等待时间;以及主动存储器处理器，其通过一个网络，存储用于处理对活动存储器操作的定制事务的代码，基于代码执行存储在共享高速缓冲存储器或共享存储器中的操作地址或数据，并将所执行的操作结果发送到处理元件。

6. 发明申请

US20110140280A1 Semiconductor apparatus capable of error revision using pin extension technique and design method therefor 有权
标题翻译：能够使用引脚扩展技术进行错误修正的半导体装置及其设计方法
公开(公告)号：US20110140280A1
公开(公告)日：2011-06-16
申请号：US12928021
申请日：2010-12-01
申请人： Dong-Yun Kim , Dong-Hoon Yeo , Hyun-Chul Shin , Kyung-Ho Kim , Byung-Tae Kang , Ju-Yong Shin , Sung-Chul Lee
发明人： Dong-Yun Kim , Dong-Hoon Yeo , Hyun-Chul Shin , Kyung-Ho Kim , Byung-Tae Kang , Ju-Yong Shin , Sung-Chul Lee
IPC分类号： H01L23/48 , G06F17/50
CPC分类号： H01L23/525 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus and a design method for the semiconductor apparatus allow debugging or repairs by using a spare cell. The semiconductor apparatus includes a plurality of metal layers. At least one repair block performs a predetermined function. A spare block is capable of substituting for a function of the repair block. And at least one of the plurality of metal layers is predetermined to be a repair layer for error revision. At least one pin of the repair block is connected to the repair layer through a first pin extension, and at least one pin of the spare block is capable of extending to the repair layer. When the repair block is to be repaired, the pin extension of the repair layer and the repair block is disconnected, and at least one pin of the spare block is connected to the repair layer through a second pin extension.
摘要翻译：半导体装置的半导体装置和设计方法允许使用备用单元进行调试或维修。半导体装置包括多个金属层。至少一个修理块执行预定的功能。备用块能够代替维修块的功能。并且多个金属层中的至少一个被预先确定为用于错误修正的修复层。修复块的至少一个销通过第一销延伸连接到修复层，并且备用块的至少一个引脚能够延伸到修复层。当修理修理块时，修理层和维修块的销延伸被断开，备用块的至少一个引脚通过第二个引脚延伸连接到修复层。

7. 发明授权

US07732317B2 Methods of forming contact structures for memory cells using both anisotropic and isotropic etching 有权
标题翻译：使用各向异性和各向同性蚀刻形成存储单元的接触结构的方法
公开(公告)号：US07732317B2
公开(公告)日：2010-06-08
申请号：US10899226
申请日：2004-07-26
申请人： Hyun-Chul Shin , Jeong-Ho Park , Jung-Young Lee , Kwang-Won Park
发明人： Hyun-Chul Shin , Jeong-Ho Park , Jung-Young Lee , Kwang-Won Park
IPC分类号： H01L21/4763
CPC分类号： H01L27/11521 , H01L21/76831 , H01L21/76897 , H01L27/115
摘要： Methods of forming a cell of a NOR-type flash memory device are provided in which a first gate pattern having a first sidewall and a second gate pattern having a second sidewall that opposes the first sidewall are formed on a semiconductor substrate. A source/drain region is formed in the semiconductor substrate between the first and second gate patterns. An etch stop layer is formed on the first and second sidewalls that defines a gap region. A dielectric layer is formed in the gap region, and is then etched to form a contact hole. Finally, a conductive material is deposited in the contact hole.
摘要翻译：提供了形成NOR型闪存器件的单元的方法，其中在半导体衬底上形成具有第一侧壁的第一栅极图案和具有与第一侧壁相对的第二侧壁的第二栅极图案。源极/漏极区域形成在第一和第二栅极图案之间的半导体衬底中。在限定间隙区域的第一和第二侧壁上形成蚀刻停止层。在间隙区域形成电介质层，然后进行蚀刻以形成接触孔。最后，导电材料沉积在接触孔中。

8. 发明申请

US20050140002A1 Methods of forming contact structures for memory cells using etch stop layers and related devices 有权
标题翻译：使用蚀刻停止层和相关器件形成存储器单元的接触结构的方法
公开(公告)号：US20050140002A1
公开(公告)日：2005-06-30
申请号：US10899226
申请日：2004-07-26
申请人： Hyun-Chul Shin , Jeong-Ho Park , Jung-Young Lee , Kwang-Won Park
发明人： Hyun-Chul Shin , Jeong-Ho Park , Jung-Young Lee , Kwang-Won Park
IPC分类号： H01L21/28 , H01L21/60 , H01L21/8242 , H01L21/8247 , H01L23/48 , H01L27/115 , H01L29/76 , H01L31/062
CPC分类号： H01L27/11521 , H01L21/76831 , H01L21/76897 , H01L27/115
摘要： Methods of forming a cell of a NOR-type flash memory device are provided in which a first gate pattern having a first sidewall and a second gate pattern having a second sidewall that opposes the first sidewall are formed on a semiconductor substrate. A source/drain region is formed in the semiconductor substrate between the first and second gate patterns. An etch stop layer is formed on the first and second sidewalls that defines a gap region. A dielectric layer is formed in the gap region, and is then etched to form a contact hole. Finally, a conductive material is deposited in the contact hole.
摘要翻译：提供了形成NOR型闪存器件的单元的方法，其中在半导体衬底上形成具有第一侧壁的第一栅极图案和具有与第一侧壁相对的第二侧壁的第二栅极图案。源极/漏极区域形成在第一和第二栅极图案之间的半导体衬底中。在限定间隙区域的第一和第二侧壁上形成蚀刻停止层。在间隙区域形成电介质层，然后进行蚀刻以形成接触孔。最后，导电材料沉积在接触孔中。

9. 发明申请

US20050032186A1 Regulatory zinc finger proteins 审中-公开
标题翻译：调节锌指蛋白
公开(公告)号：US20050032186A1
公开(公告)日：2005-02-10
申请号：US10732620
申请日：2003-12-09
申请人： Jin-Soo Kim , Hyun-Chul Shin , Heung-Sun Kwon
发明人： Jin-Soo Kim , Hyun-Chul Shin , Heung-Sun Kwon
IPC分类号： C07K14/47 , C07K19/00 , C12N15/29 , C12Q1/68 , C07H21/04 , C12N9/22
CPC分类号： C07K14/475 , C07K14/4702
摘要： Disclosed are chimeric zinc finger proteins that can regulate endogenous genes. Examples of such proteins include proteins that can regulate VEGF-A expression. The proteins and nucleic acid encoding them can be used to modulate angiogenesis.
摘要翻译：公开了可调节内源基因的嵌合锌指蛋白。这些蛋白质的实例包括可以调节VEGF-A表达的蛋白质。编码它们的蛋白质和核酸可用于调节血管发生。

10. 发明授权

US08689163B2 Semiconductor apparatus capable of error revision using pin extension technique and design method therefor 有权
标题翻译：能够使用引脚扩展技术进行错误修正的半导体装置及其设计方法
公开(公告)号：US08689163B2
公开(公告)日：2014-04-01
申请号：US12928021
申请日：2010-12-01
申请人： Dong-Yun Kim , Dong-Hoon Yeo , Hyun-Chul Shin , Kyung-Ho Kim , Byung-Tae Kang , Ju-Yong Shin , Sung-Chul Lee
发明人： Dong-Yun Kim , Dong-Hoon Yeo , Hyun-Chul Shin , Kyung-Ho Kim , Byung-Tae Kang , Ju-Yong Shin , Sung-Chul Lee
IPC分类号： G06F17/50
CPC分类号： H01L23/525 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus and a design method for the semiconductor apparatus allow debugging or repairs by using a spare cell. The semiconductor apparatus includes a plurality of metal layers. At least one repair block performs a predetermined function. A spare block is capable of substituting for a function of the repair block. And at least one of the plurality of metal layers is predetermined to be a repair layer for error revision. At least one pin of the repair block is connected to the repair layer through a first pin extension, and at least one pin of the spare block is capable of extending to the repair layer. When the repair block is to be repaired, the pin extension of the repair layer and the repair block is disconnected, and at least one pin of the spare block is connected to the repair layer through a second pin extension.
摘要翻译：半导体装置的半导体装置和设计方法允许使用备用单元进行调试或维修。半导体装置包括多个金属层。至少一个修理块执行预定的功能。备用块能够代替维修块的功能。并且多个金属层中的至少一个被预先确定为用于错误修正的修复层。修复块的至少一个销通过第一销延伸连接到修复层，并且备用块的至少一个引脚能够延伸到修复层。当修理修理块时，修理层和维修块的销延伸被断开，备用块的至少一个引脚通过第二个引脚延伸连接到修复层。

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