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1. 发明申请

US20160224319A1 HIGH-SPEED THREE-OPERAND N-BIT ADDER 审中-公开
标题翻译：高速三位一体式N位加法器
公开(公告)号：US20160224319A1
公开(公告)日：2016-08-04
申请号：US14610739
申请日：2015-01-30
申请人： Huong HO , Michel Kafrouni
发明人： Huong HO , Michel Kafrouni
IPC分类号： G06F7/509
CPC分类号： G06F7/509
摘要： An adder and a method for calculating a sum of three input operands. The adder comprises a pre-processor, a generator and a post-processor. The pre-processor creates an initial propagation vector having a plurality of bit-positions, each bit-position in the plurality representing whether a carry in bit is propagated as a carry out bit as determined from a value of respective bit-positions of each of the three operands. The pre-processor creates an initial generation vector having a plurality of bit-positions, each bit-position in the plurality representing whether a carry out bit is generated as determined from a value of respective bit-positions of each of the three operands. The generator generates a composite propagation vector and a composite generation vector from parallel prefix operations on the initial propagation vector and initial generation vector. The post-processor calculates the sum from the initial propagation vector, the composite propagation vector and the composite generation vector. The adder has a gate delay of 2 log2(N)+4.
摘要翻译：一种用于计算三个输入操作数之和的加法器和方法。加法器包括预处理器，发生器和后处理器。预处理器创建具有多个位位置的初始传播向量，多个位位置中的每个位位置表示进位位是否作为进位位传播，如从每个的相应位位置的值确定的三个操作数。预处理器创建具有多个比特位置的初始生成向量，多个比特位置表示根据三个操作数中的每一个的相应比特位的值来生成进位比特。生成器从初始传播向量和初始生成向量的并行前缀操作生成复合传播向量和复合生成向量。后处理器计算从初始传播向量，复合传播向量和复合生成向量的和。加法器的门延迟为2log2（N）+4。

2. 发明申请

US20160224318A1 METHOD AND APPARATUS FOR CONVERTING FROM INTEGER TO FLOATING POINT REPRESENTATION 审中-公开
标题翻译：从整数到浮点表示的方法和装置
公开(公告)号：US20160224318A1
公开(公告)日：2016-08-04
申请号：US14610029
申请日：2015-01-30
申请人： Huong HO , Michel KAFROUNI
发明人： Huong HO , Michel KAFROUNI
IPC分类号： G06F5/01 , H03M7/30
CPC分类号： G06F5/012 , H03M7/24 , H03M7/28
摘要： Apparatus and methods for conversion from signed integer to a floating point representation are provided. Two's complementation and lead zero count operations are performed in parallel. Exponent generation and mantissa shifting are performed in parallel. Generation of the floating point exponent from the signed integer, including application of a scaling factor, is performed using a 3:2 compressor or carry-save adder and an adder. Two's complementation for generation of the mantissa in unsigned integer format is performed using an adder. Lead zero count for controlling mantissa shifting is performed by one's complementing the signed integer if negative, counting lead zeros in the one's complement output, and determining, using the one's complement output, whether the one's complement lead zero count differs from the two's complement lead zero count by one.
摘要翻译：提供了从有符号整数转换为浮点表示的装置和方法。二进制补码和引导零计数操作并行执行。并行执行指数生成和尾数移位。使用3：2压缩器或进位存储加法器和加法器来执行从带符号整数生成浮点指数，包括缩放因子的应用。使用加法器执行用于以无符号整数格式生成尾数的二进制补码。用于控制尾数移位的引导零计数是通过补码有符号整数进行补码，如果为负，则在补码输出中计数前导零，并且使用补码输出来确定补码导数零计数是否与二进制补零引线零点不同算一个

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