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1. 发明授权

US06202130B1 Data processing system for processing vector data and method therefor 失效
标题翻译：用于处理矢量数据的数据处理系统及其方法
公开(公告)号：US06202130B1
公开(公告)日：2001-03-13
申请号：US09061975
申请日：1998-04-17
申请人： Hunter Ledbetter Scales, III , Keith Everett Diefendorff , Brett Olsson , Pradeep Kumar Dubey , Ronald Ray Hochsprung , Bradford Byron Beavers , Bradley G. Burgess , Michael Dean Snyder , Cathy May , Edward John Silha
发明人： Hunter Ledbetter Scales, III , Keith Everett Diefendorff , Brett Olsson , Pradeep Kumar Dubey , Ronald Ray Hochsprung , Bradford Byron Beavers , Bradley G. Burgess , Michael Dean Snyder , Cathy May , Edward John Silha
IPC分类号： G06F1200
CPC分类号： G06F9/30047 , G06F9/30101 , G06F12/0862 , G06F2212/6028
摘要： A data processing system includes a data processor (10) coupled to a memory system having a first memory, such as an L1 data cache (16), arranged with a second memory (such as an L2 cache) at a lower hierarchical level. The data processor (10) prefetches data elements of a vector into the first memory prior to processing such data elements. If a requested data element is not present in the first memory, a load request is issued to the second memory and to lower levels of the memory hierarchy until the requested data element is finally retrieved and stored in the first memory. The data processor (10) continues to prefetch subsequent data elements of the vector by considering the length of the data element and the stride of the vector. In one embodiment, the data processor (10) prefetches the vector into the first memory in response to a single data stream touch load (DST) instruction (100).
摘要翻译：数据处理系统包括耦合到具有诸如L1数据高速缓存（16）的第一存储器的存储器系统的数据处理器（10），其布置在较低分层级的第二存储器（例如L2高速缓存）。在处理这些数据元素之前，数据处理器（10）将向量的数据元素预取到第一存储器中。如果请求的数据元素不存在于第一存储器中，则向第二存储器发出加载请求，并将存储器层级降低到最低限度，直到所请求的数据元素被最终检索并存储在第一存储器中。数据处理器（10）通过考虑数据元素的长度和向量的步幅继续预取向量的后续数据元素。在一个实施例中，数据处理器（10）响应于单个数据流接触负载（DST）指令（100）将矢量预取到第一存储器中。

2. 发明授权

US06499116B1 Performance of data stream touch events 失效
标题翻译：数据流触摸事件的性能
公开(公告)号：US06499116B1
公开(公告)日：2002-12-24
申请号：US09282694
申请日：1999-03-31
申请人： Charles Philip Roth , Michael Dean Snyder
发明人： Charles Philip Roth , Michael Dean Snyder
IPC分类号： G06F1100
CPC分类号： G06F9/384 , G06F9/30047 , G06F9/3455 , G06F9/383 , G06F9/3857 , G06F11/3409 , G06F11/3414 , G06F11/348 , G06F12/0862 , G06F2201/86 , G06F2201/865 , G06F2201/88 , G06F2201/885 , G06F2212/6028
摘要： Data stream touch instructions are software-directed asynchronous prefetch instructions that can improve the performance of a system. Ideally, such instructions are used in perfect synchronization with the actual memory fetches that are trying to speed up. In practical situations, it is difficult to predict ahead of time all side effects of these instructions and memory access latency/throughput during execution of any large program. Incorrect usage of such instructions can cause degraded performance of the system. Thus, it is advantageous to measure the performance of such instructions.
摘要翻译：数据流触摸指令是可以提高系统性能的软件定向异步预取指令。理想情况下，这些指令用于与正试图加快的实际内存提取的完美同步。在实际情况下，难以在执行任何大型程序时提前预测这些指令和内存访问延迟/吞吐量的所有副作用。不正确使用此类指令可能导致系统性能下降。因此，测量这些指令的性能是有利的。

3. 发明授权

US06311254B1 Multiple store miss handling in a cache memory memory system 失效
标题翻译：缓存存储系统中的多个存储错误处理
公开(公告)号：US06311254B1
公开(公告)日：2001-10-30
申请号：US09271494
申请日：1999-03-18
申请人： Belliappa Manavattira Kuttanna , Rajesh Patel , Michael Dean Snyder
发明人： Belliappa Manavattira Kuttanna , Rajesh Patel , Michael Dean Snyder
IPC分类号： G06F1200
CPC分类号： G06F12/0859
摘要： A cache memory system including a cache memory suitable for coupling to a load/store unit of a CPU, a buffer unit comprised of a plurality of entries each including a data buffer and a corresponding address tag. The system is configured to initiate a data fetch transaction in response to a first store operation that misses in both the cache memory and the buffer unit, to allocate a first entry in the buffer unit, and to write the first store operation's data in the first entry's data buffer. The system is adapted to write data from at least one subsequent store operation into the first entry's data buffer if the subsequent store operation misses in the cache but hits in the first entry of the buffer unit prior to completion of the data fetch transaction. In this manner, the first entry's data buffer includes a composite of the first and subsequent store operations' data. Preferably, the cache system is further configured to merge, upon completion of the data fetch, the fetched data with the store operation data in the first entry's data buffer and to reload the cache memory from the first entry's data buffer. In the preferred embodiment, each buffer unit entry further includes data valid bits that indicate the validity of corresponding portions of the entry's data buffer. In this embodiment, the buffer unit is preferably configured to reload the cache memory from the first buffer unit entry if all of the first entry's data valid bits are set prior to completion of the data fetch transaction thereby affecting a “silent” reload of the cache memory in which no data is ultimately required from memory.
摘要翻译：一种高速缓冲存储器系统，包括适于耦合到CPU的加载/存储单元的高速缓冲存储器，由包括数据缓冲器和相应的地址标签的多个条目组成的缓冲器单元。该系统被配置为响应于在高速缓冲存储器和缓冲器单元中丢失的第一存储操作来发起数据提取事务，以在缓冲器单元中分配第一条目，并将第一存储操作的数据写入第一存储操作的第一存储操作条目的数据缓冲区。如果随后的存储操作在高速缓存中错过但在数据提取事务完成之前在缓冲单元的第一条目中命中，则系统适于将数据从至少一个后续存储操作写入到第一条目的数据缓冲器中。以这种方式，第一条目的数据缓冲器包括第一和后续存储操作数据的组合。优选地，高速缓存系统还被配置为在数据获取完成时，将获取的数据与第一条目的数据缓冲器中的存储操作数据进行合并，并从第一条目的数据缓冲器重新加载高速缓冲存储器。在优选实施例中，每个缓冲器单元条目还包括指示条目的数据缓冲器的对应部分的有效性的数据有效位。在该实施例中，缓冲单元优选地被配置为如果在完成数据提取事务之前设置了所有第一条目的数据有效位，从而影响高速缓存的“无声”重新加载，则从第一缓冲单元条目重新加载高速缓冲存储器内存最终不需要内存的内存。

4. 发明授权

US06321303B1 Dynamically modifying queued transactions in a cache memory system 失效
标题翻译：动态修改缓存内存系统中的排队事务
公开(公告)号：US06321303B1
公开(公告)日：2001-11-20
申请号：US09271492
申请日：1999-03-18
申请人： Thomas Alan Hoy , Belliappa Manavattira Kuttanna , Rajesh Patel , Michael Dean Snyder
发明人： Thomas Alan Hoy , Belliappa Manavattira Kuttanna , Rajesh Patel , Michael Dean Snyder
IPC分类号： G06F1208
CPC分类号： G06F12/0831
摘要： A computer and its corresponding cache system includes a cache memory, a buffer unit, and a bus transaction queue. The buffer unit includes a plurality of entries suitable for temporarily storing data, address, and attribute information of operations generated by the CPU. A first operation initiated by the load store unit buffers an operation in a first entry of the buffer unit, which initiates a first transaction to be queued in a first entry of the bus transaction queue where the first transaction in the bus transaction queue points to the first entry in the buffer unit. Preferably, the buffer unit is configured to modify the first transaction from a first transaction type to a second transaction type prior to execution in response to an event that alters the data requirements of the queued transaction. Additional utility is achieved by merging multiple store operation that miss to a common cache line into a single entry. Further benefits is achieved by allowing multiple load misses to the same cache line to be completed from a buffer that reduces cache pipeline stalls.
摘要翻译：计算机及其对应的缓存系统包括高速缓冲存储器，缓冲器单元和总线事务队列。缓冲单元包括适于临时存储由CPU生成的操作的数据，地址和属性信息的多个条目。由加载存储单元启动的第一操作缓冲在缓冲单元的第一条目中的操作，该操作启动要在总线事务队列的第一条目中排队的第一事务，其中总线事务队列中的第一事务指向缓冲单元中的第一个条目。优选地，缓冲单元被配置为响应于改变排队交易的数据需求的事件，在执行之前将第一事务从第一事务类型修改为第二事务类型。通过将多个存储操作错过公用高速缓存行合并到单个条目中来实现附加效用。通过允许从减少高速缓存管道停顿的缓冲器中完成相同高速缓存行的多个加载错误来实现进一步的益处。

5. 发明授权

US6119203A Mechanism for sharing data cache resources between data prefetch operations and normal load/store operations in a data processing system 失效
标题翻译：在数据处理系统中，在数据预取操作与正常加载/存储操作之间共享数据缓存资源的机制
公开(公告)号：US6119203A
公开(公告)日：2000-09-12
申请号：US127883
申请日：1998-08-03
申请人： Michael Dean Snyder , Rajesh Patel
发明人： Michael Dean Snyder , Rajesh Patel
IPC分类号： G06F9/312 , G06F9/38 , G06F12/08
CPC分类号： G06F9/30043 , G06F12/0862 , G06F9/30047 , G06F9/3455 , G06F9/383 , G06F2212/6028
摘要： A data processing system (10) provides a mechanism for choosing when the data stream touch (DST) controller (300) is allowed access to the data cache and MMU (50). The mechanism uses a count value to determine at what point in program execution the DST controller (300) is allowed to interrupt normal load and store accesses. This allows DST prefetches to be optimized for maximum performance of the data processing system (10).
摘要翻译：数据处理系统（10）提供用于选择何时数据流触摸（DST）控制器（300）被允许访问数据高速缓存和MMU（50）的机制。该机制使用计数值来确定程序执行的时间点DST控制器（300）允许中断正常加载和存储访问。这样可以对数据处理系统（10）的最大性能优化DST预取。

6. 发明授权

US06269427B1 Multiple load miss handling in a cache memory system 有权
标题翻译：高速缓冲存储器系统中的多次错误处理
公开(公告)号：US06269427B1
公开(公告)日：2001-07-31
申请号：US09271493
申请日：1999-03-18
申请人： Belliappa Manavattira Kuttanna , Rajesh Patel , Michael Dean Snyder
发明人： Belliappa Manavattira Kuttanna , Rajesh Patel , Michael Dean Snyder
IPC分类号： G06F1208
CPC分类号： G06F9/30043 , G06F9/30047 , G06F9/3824 , G06F12/0831 , G06F12/0859
摘要： A cache memory system including a cache memory configured for coupling to a load/store unit of a CPU, a buffer unit coupled to said cache memory, and an operation queue comprising a plurality of entries, wherein each valid operation queue entry points to an entry in the buffer unit. The buffer unit includes a plurality of data buffers and each of the data buffers is associated with a corresponding address tag. The system is configured to initiate a data fetch transaction and allocate an entry in the buffer unit in response to a CPU load operation that misses in both the cache memory and the buffer unit. The cache system is further configured to allocate entries in the operation queue in response to subsequent CPU load operations that miss in the cache memory but hit in the buffer unit prior to completion of the data fetch. Preferably, the system is configured to store the fetched data in the buffer unit entry upon satisfaction of said data fetch and still further configured to satisfy pending load operations in the operation queue from the buffer unit entry. In the preferred embodiment, the system is configured to reload the. cache memory from the buffer unit entry upon satisfying all operation queue entries pointing to the buffer unit entry and, thereafter, to invalidate the buffer unit entry and the operation queue entries. The buffer unit entries preferably each include data valid bits indicative of which portions of data stored in a buffer unit entry are valid.
摘要翻译：一种高速缓冲存储器系统，包括被配置为耦合到CPU的加载/存储单元的高速缓存存储器，耦合到所述高速缓存存储器的缓冲器单元和包括多个条目的操作队列，其中每个有效操作队列入口指向条目在缓冲单元中。缓冲单元包括多个数据缓冲器，并且每个数据缓冲器与相应的地址标签相关联。该系统被配置为响应于在高速缓冲存储器和缓冲器单元中丢失的CPU加载操作而发起数据提取事务并在缓冲器单元中分配条目。高速缓存系统还被配置为响应于在高速缓冲存储器中错过的随后的CPU加载操作来在操作队列中分配条目，而在数据提取完成之前在缓冲器单元中命中。优选地，系统被配置为在满足所述数据提取时将获取的数据存储在缓冲器单元条目中，并且还被配置为满足来自缓冲器单元条目的操作队列中的未决加载操作。在优选实施例中，系统被配置为重新加载。满足指向缓冲单元条目的所有操作队列条目，然后使缓冲单元条目和操作队列条目无效，从缓冲单元条目缓存存储器。缓冲单元条目优选地每个都包括指示存储在缓冲单元条目中的数据的哪些部分有效的数据有效位。

7. 发明授权

US6163835A Method and apparatus for transferring data over a processor interface bus 失效
标题翻译：用于通过处理器接口总线传送数据的方法和装置
公开(公告)号：US6163835A
公开(公告)日：2000-12-19
申请号：US110351
申请日：1998-07-06
申请人： David William Todd , Michael Dean Snyder , Brian Keith Reynolds , Michael Julio Garcia
发明人： David William Todd , Michael Dean Snyder , Brian Keith Reynolds , Michael Julio Garcia
IPC分类号： G06F13/36 , G06F12/08 , G06F13/16 , G06F13/38 , G06F13/42 , G06F15/17 , G06F15/16
CPC分类号： G06F12/0833 , G06F15/17
摘要： A method of transferring data between a slave device (20) in communication with a processor interface bus (34) where the processor interface bus is in communication with a master device (12) including receiving an address from the processor interface bus (34) where the address was provided by the master device (block 302). A first signal is asserted (blocks 318 and 324) on the processor interface bus (34) to indicate that the slave device (20) is servicing a data transfer transaction. A second signal is asserted (block 320) on the processor interface bus (34) to indicate whether data to be transferred using the processor interface bus (34) is to be stored in main memory (36) by a main memory controller (32) in communication with the processor interface bus (34). The data is transferred (block 326) between the slave device (20) and the processor interface bus (34).
摘要翻译：一种在与处理器接口总线（34）通信的从设备（20）之间传送数据的方法，其中处理器接口总线与主设备（12）通信，包括从处理器接口总线（34）接收地址，其中处理器接口总线地址由主设备提供（框302）。处理器接口总线（34）上的第一信号被断言（框318和324）以指示从设备（20）正在服务于数据传输事务。在处理器接口总线（34）上确定第二信号（方框320），以指示是否将使用处理器接口总线（34）传输的数据由主存储器控制器（32）存储在主存储器（36）与处理器接口总线（34）通信。在从设备（20）和处理器接口总线（34）之间传送数据（方框326）。

8. 发明授权

US6073215A Data processing system having a data prefetch mechanism and method therefor 有权
标题翻译：数据处理系统具有数据预取机制及其方法
公开(公告)号：US6073215A
公开(公告)日：2000-06-06
申请号：US127884
申请日：1998-08-03
申请人： Michael Dean Snyder
发明人： Michael Dean Snyder
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0859 , G06F2212/6028
摘要： A data processing system (10) includes a mechanism for preventing DST line fetches from occupying the last available entries in a cache miss queue (50) of the data cache and MMU (16). This is done by setting a threshold value of available cache miss queue (50) buffers over which a DST access is not allowed. This prevents the cache miss queue (50) from filling up and preventing normal load and store accesses from using the cache miss queue (50).
摘要翻译：数据处理系统（10）包括用于防止DST线取出占据数据高速缓存和MMU（16）的高速缓存未命中队列（50）中的最后可用条目的机制。这是通过设置不允许DST访问的可用缓存未命中队列（50）缓冲区的阈值来完成的。这防止高速缓存未命中队列（50）填满并防止正常加载并存储访问以使用高速缓存未命中队列（50）。

9. 发明授权

US06785772B2 Data prefetching apparatus in a data processing system and method therefor 有权
标题翻译：数据处理系统中的数据预取装置及其方法
公开(公告)号：US06785772B2
公开(公告)日：2004-08-31
申请号：US10132918
申请日：2002-04-26
申请人： Suresh Venkumahanti , Michael Dean Snyder
发明人： Suresh Venkumahanti , Michael Dean Snyder
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F9/30047 , G06F9/3455 , G06F9/383 , G06F2212/6028
摘要： A data processing system (20) is able to perform parameter-selectable prefetch instructions to prefetch data for a cache (38). When attempting to be backward compatible with previously written code, sometimes performing this instruction can result in attempting to prefetch redundant data by prefetching the same data twice. In order to prevent this, the parameters of the instruction are analyzed to determine if such redundant data will be prefetched. If so, then the parameters are altered to avoid prefetching redundant data. In some of the possibilities for the parameters of the instruction, the altering of the parameters requires significant circuitry so that an alternative approach is used. This alternative but slower approach, which can be used in the same system with the first approach, detects if the line of the cache that is currently being requested is the same as the previous request. If so, the current request is not executed.
摘要翻译：数据处理系统（20）能够执行参数可选择的预取指令以预取高速缓存（38）的数据。当尝试向后兼容以前写入的代码时，有时执行此指令可能会导致尝试通过预取相同数据两次来预取冗余数据。为了防止这种情况，分析指令的参数以确定是否将预取这样的冗余数据。如果是这样，则修改参数以避免预取冗余数据。在指令参数的一些可能性中，参数的更改需要大量的电路，以便使用另外的方法。可以在与第一种方法相同的系统中使用的这种替代但较慢的方法检测当前正在请求的高速缓存行是否与先前请求相同。如果是，则不执行当前请求。

10. 发明授权

US06240479B1 Method and apparatus for transferring data on a split bus in a data processing system 失效
标题翻译：用于在数据处理系统中的分离总线上传送数据的方法和装置
公开(公告)号：US06240479B1
公开(公告)日：2001-05-29
申请号：US09127459
申请日：1998-07-31
申请人： Michael Dean Snyder , David William Todd , Brian Keith Reynolds , Michael Julio Garcia
发明人： Michael Dean Snyder , David William Todd , Brian Keith Reynolds , Michael Julio Garcia
IPC分类号： G06F13362
CPC分类号： G06F13/364
摘要： A bus protocol for a split bus (50, 60) where each device (10, 20, 30) coupled to the bus has an age-based queue (12, 24, 34) of pending transactions. Queues are updated as transactions are executed. A central arbiter (40) has a copy of each device's queue (44). A priority transaction is determined from among all the queues in the arbiter. A data transaction index (DTI) is broadcast during the data tenure to all devices indicating the position in the queue of the next transaction. The index allows out-of-order data transfers without the provision of a static tag during the address tenure. Queues maintain a history of pending transactions. In one embodiment, each device receives a separate data bus grant (DBG), allowing a single provision of the index to both a source and a sink device.
摘要翻译：一种用于分离总线（50,60）的总线协议，其中耦合到所述总线的每个设备（10,20,30）具有未决事务的基于年龄的队列（12,24,34）。队列随着交易的执行而更新。中央仲裁器（40）具有每个设备队列的副本（44）。从仲裁器中的所有队列中确定优先级事务。数据交换索引（DTI）在数据期间广播到所有设备，指示下一个事务的队列中的位置。该索引允许在地址持有期间不提供静态标签的无序数据传输。队列保留待处理交易的历史。在一个实施例中，每个设备接收单独的数据总线许可（DBG），允许向源设备和宿设备单独提供索引。

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