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1. 发明申请

US20060143319A1 METHOD OF ESTABLISHING COMMUNICATION BETWEEN A USB DEVICE AND A HOST 审中-公开
标题翻译：在USB设备和主机之间建立通信的方法
公开(公告)号：US20060143319A1
公开(公告)日：2006-06-29
申请号：US11161989
申请日：2005-08-25
申请人： Hung-Yuan Hsu , Shih-Feng Huang , Chien-Hsing Hsieh , Ching-Lin Chung , Guo-Yuan Ma
发明人： Hung-Yuan Hsu , Shih-Feng Huang , Chien-Hsing Hsieh , Ching-Lin Chung , Guo-Yuan Ma
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： A method for establishing communication between a USB having a first memory device and a second memory device and a host includes reading first USB identification data stored in the first memory device, determining if the USB device can communicate with the host based on the first USB identification data, and reading second USB identification data stored in the second memory device for establishing communication between the USB device and the host if the USB device cannot communicate with the host based on the first USB identification data.
摘要翻译：一种用于建立具有第一存储设备和第二存储设备的USB与主机之间的通信的方法，包括读取存储在第一存储设备中的第一USB识别数据，确定USB设备是否可以基于第一USB标识与主机通信数据和读取存储在第二存储器设备中的第二USB识别数据，用于在USB设备不能基于第一USB识别数据与主机通信时建立USB设备与主机之间的通信。

2. 发明申请

US20060159209A1 MULTI-PIPE SYNCHRONIZER SYSTEM 审中-公开
标题翻译：多管同步系统
公开(公告)号：US20060159209A1
公开(公告)日：2006-07-20
申请号：US10905725
申请日：2005-01-18
申请人： Hung-Yuan Hsu , Ching-Lin Chung
发明人： Hung-Yuan Hsu , Ching-Lin Chung
IPC分类号： H04L7/00
CPC分类号： H04L7/02
摘要： A multi-pipe synchronizer system includes at least two synchronizers for receiving a source signal and corresponding source clock, and a destination clock. A switch is coupled to an input of each synchronizer for coupling the source signal to a selected synchronizer. A generator is coupled to an output of each synchronizer. The generator is for merging output of the synchronizers into a destination signal corresponding to the destination clock.
摘要翻译：多管同步器系统包括用于接收源信号和对应的源时钟的至少两个同步器以及目的地时钟。开关耦合到每个同步器的输入，用于将源信号耦合到所选择的同步器。发电机耦合到每个同步器的输出端。发生器用于将同步器的输出合并成与目的地时钟对应的目的地信号。

3. 发明申请

US20070083685A1 Data management for a USB device 审中-公开
标题翻译： USB设备的数据管理
公开(公告)号：US20070083685A1
公开(公告)日：2007-04-12
申请号：US11248942
申请日：2005-10-11
申请人： Hung-Yuan Hsu , Ching-Lin Chung , Ho Le-Chun , Chien-Hsing Hsieh
发明人： Hung-Yuan Hsu , Ching-Lin Chung , Ho Le-Chun , Chien-Hsing Hsieh
IPC分类号： G06F13/38
CPC分类号： G06F13/38
摘要： A data management method for a USB device includes the steps of: sampling an analog input signal, and generating digital sample data corresponding to samples of the analog input signal; monitoring the number of the digital sample data generated within a predefined time interval; if the number of the digital sample data generated at the end of the predefined time interval matches a predetermined value, providing the digital sample data to a USB host; and if the number of the digital sample data generated at the end of the predefined time interval does not match the predetermined value, processing the digital sample data such that the number of the processed digital sample data matches the predetermined value, and providing the processed digital sample data to the USB host. A USB device including a data management module for implementing the data management method is also disclosed.
摘要翻译：一种用于USB设备的数据管理方法包括以下步骤：对模拟输入信号进行采样，并产生与模拟输入信号的采样对应的数字采样数据; 监视在预定时间间隔内生成的数字样本数据的数量; 如果在预定时间间隔结束时产生的数字样本数据的数量与预定值相匹配，则将数字样本数据提供给USB主机; 并且如果在预定时间间隔结束时生成的数字样本数据的数量与预定值不匹配，则处理数字样本数据，使得经处理的数字样本数据的数量与预定值相匹配，并且提供经处理的数字将数据采样到USB主机。还公开了一种包括用于实现数据管理方法的数据管理模块的USB装置。

4. 发明申请

US20060198479A1 DATA SYNCHRONIZER SYSTEM 审中-公开
标题翻译：数据同步系统
公开(公告)号：US20060198479A1
公开(公告)日：2006-09-07
申请号：US10906677
申请日：2005-03-01
申请人： Hung-Yuan Hsu , Ching-Lin Chung
发明人： Hung-Yuan Hsu , Ching-Lin Chung
IPC分类号： H04L7/00
CPC分类号： H04L7/0012 , H04L7/0037
摘要： A data synchronizer system includes at least two synchronizers for receiving a source pulse signal, a corresponding source clock, and a destination clock. At least two first memory units each have a destination clock input. A first switch has an input coupled to the source pulse signal and an output selectively coupled to a source pulse signal input of any one of the synchronizers. A second memory unit has an input coupled to the source data signal and a clock input coupled to the source clock. A second switch has an input coupled to an output of the second memory unit and an output selectively coupled to an input of any one of the first memory units. A generator is coupled to outputs of the synchronizers for outputting a data switch signal. A multiplexer has inputs coupled to outputs of the first memory units and outputs a destination data signal.
摘要翻译：数据同步器系统包括用于接收源脉冲信号，对应源时钟和目的时钟的至少两个同步器。至少两个第一存储器单元各自具有目的地时钟输入。第一开关具有耦合到源极脉冲信号的输入和选择性地耦合到任一个同步器的源极脉冲信号输入的输出。第二存储器单元具有耦合到源数据信号的输入和耦合到源时钟的时钟输入。第二开关具有耦合到第二存储器单元的输出的输入和选择性地耦合到第一存储器单元中的任何一个的输入的输出。发生器耦合到同步器的输出端，用于输出数据开关信号。多路复用器具有耦合到第一存储器单元的输出并输出目的地数据信号的输入。

5. 发明授权

US08097491B1 Chip structure having redistribution layer and fabrication method thereof 有权
标题翻译：具有再分布层的芯片结构及其制造方法
公开(公告)号：US08097491B1
公开(公告)日：2012-01-17
申请号：US12962326
申请日：2010-12-07
申请人： Hung-Yuan Hsu , Sui-An Kao
发明人： Hung-Yuan Hsu , Sui-An Kao
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44
CPC分类号： H01L23/3171 , H01L24/02 , H01L2224/0235 , H01L2224/02377 , H01L2224/0239 , H01L2224/024 , H01L2924/01005 , H01L2924/01006 , H01L2924/01079
摘要： A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer.
摘要翻译：具有再分配层的芯片结构包括：具有设置在其活性表面上的电极焊盘的芯片; 形成在所述有源表面和所述电极焊盘上的第一钝化层; 形成在所述第一钝化层上并具有多个布线单元的再分配层，其中每个所述布线单元具有导电焊盘，导电孔和连接所述导电焊盘和所述导电通孔的导电迹线，所述导电迹线至少具有用于暴露第一钝化层的一部分的第一通孔; 以及设置在所述第一钝化层和所述再分布层上的第二钝化层，所述第二钝化层填充在所述第一通孔中，使得所述第一钝化层和所述第二钝化层彼此接合，导电迹线夹在其间，从而防止分层的来自第二钝化层的导电迹线。

6. 发明授权

US5308897A Degradable plastics 失效
标题翻译：可降解塑料
公开(公告)号：US5308897A
公开(公告)日：1994-05-03
申请号：US4548
申请日：1993-01-14
申请人： Hung-Yuan Hsu , Shu-Chieh Liuo , Shu-Fang Jiang , Jian-Hong Chen , Ho-May Lin , Herng-Dar Hwu , Muh-Lan Chen , Mao-Song Lee , Teh Hu
发明人： Hung-Yuan Hsu , Shu-Chieh Liuo , Shu-Fang Jiang , Jian-Hong Chen , Ho-May Lin , Herng-Dar Hwu , Muh-Lan Chen , Mao-Song Lee , Teh Hu
IPC分类号： C08K5/14 , C08L3/02 , C08L101/00 , C08L3/00
CPC分类号： C08K5/14 , C08L101/00 , C08L2201/06 , C08L3/02
摘要： A composition of matter including a polymeric material which is either a plastic having carbon to carbon linkages or a binary blend of the plastic and starch, in which the plastic is at least 25% by weight of the binary blend; and an organic peracid compound dispersed in the polymeric material, the quantity of the peracid compound being 0.1 to 10% by weight of the polymeric material.
摘要翻译：一种物质组合物，其包括聚合材料，其是具有碳 - 碳键的塑料或塑料和淀粉的二元共混物，其中塑料是二元共混物的至少25重量％和分散在聚合物材料中的有机过酸化合物，过酸化合物的量为聚合物材料的0.1-10重量％。

7. 发明授权

US08772922B2 Chip structure having redistribution layer 有权
标题翻译：具有再分配层的芯片结构
公开(公告)号：US08772922B2
公开(公告)日：2014-07-08
申请号：US13349051
申请日：2012-01-12
申请人： Hung-Yuan Hsu , Sui-An Kao
发明人： Hung-Yuan Hsu , Sui-An Kao
IPC分类号： H01L21/44 , H01L21/461 , H01L21/302
CPC分类号： H01L23/3171 , H01L24/02 , H01L2224/0235 , H01L2224/02377 , H01L2224/0239 , H01L2224/024 , H01L2924/01005 , H01L2924/01006 , H01L2924/01079
摘要： A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer.
摘要翻译：具有再分配层的芯片结构包括：具有设置在其活性表面上的电极焊盘的芯片; 形成在所述有源表面和所述电极焊盘上的第一钝化层; 形成在所述第一钝化层上并具有多个布线单元的再分配层，其中每个所述布线单元具有导电焊盘，导电孔和连接所述导电焊盘和所述导电通孔的导电迹线，所述导电迹线至少具有用于暴露第一钝化层的一部分的第一通孔; 以及设置在所述第一钝化层和所述再分布层上的第二钝化层，所述第二钝化层填充在所述第一通孔中，使得所述第一钝化层和所述第二钝化层彼此接合，导电迹线夹在其间，从而防止分层的来自第二钝化层的导电迹线。

8. 发明申请

US20120112363A1 CHIP STRUCTURE HAVING REDISTRIBUTION LAYER 有权
标题翻译：具有重新分配层的芯片结构
公开(公告)号：US20120112363A1
公开(公告)日：2012-05-10
申请号：US13349051
申请日：2012-01-12
申请人： Hung-Yuan Hsu , Sui-An Kao
发明人： Hung-Yuan Hsu , Sui-An Kao
IPC分类号： H01L23/48
CPC分类号： H01L23/3171 , H01L24/02 , H01L2224/0235 , H01L2224/02377 , H01L2224/0239 , H01L2224/024 , H01L2924/01005 , H01L2924/01006 , H01L2924/01079
摘要： A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer.
摘要翻译：具有再分配层的芯片结构包括：具有设置在其活性表面上的电极焊盘的芯片; 形成在所述有源表面和所述电极焊盘上的第一钝化层; 形成在所述第一钝化层上并具有多个布线单元的再分配层，其中每个所述布线单元具有导电焊盘，导电孔和连接所述导电焊盘和所述导电通孔的导电迹线，所述导电迹线至少具有用于暴露第一钝化层的一部分的第一通孔; 以及设置在所述第一钝化层和所述再分布层上的第二钝化层，所述第二钝化层填充在所述第一通孔中，使得所述第一钝化层和所述第二钝化层彼此接合，导电迹线夹在其间，从而防止分层的来自第二钝化层的导电迹线。

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