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1. 发明授权

US08212349B2 Semiconductor package having chip using copper process 有权
标题翻译：具有使用铜工艺的芯片的半导体封装
公开(公告)号：US08212349B2
公开(公告)日：2012-07-03
申请号：US12649092
申请日：2009-12-29
申请人： Hung-Hsin Hsu , Chin-Ming Hsu , Jui-Ching Hsu
发明人： Hung-Hsin Hsu , Chin-Ming Hsu , Jui-Ching Hsu
IPC分类号： H01L23/49 , H01L23/498
CPC分类号： H01L24/05 , H01L23/498 , H01L23/49866 , H01L24/27 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/05647 , H01L2224/274 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48145 , H01L2224/48227 , H01L2224/48228 , H01L2224/484 , H01L2224/48644 , H01L2224/48647 , H01L2224/48844 , H01L2224/48847 , H01L2224/73265 , H01L2224/83101 , H01L2224/83856 , H01L2224/85444 , H01L2225/06506 , H01L2225/0651 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2924/00011 , H01L2224/45099
摘要： A semiconductor package having chip using copper process is revealed. A chip using copper process is disposed on a substrate. The substrate has a core layer, a copper circuitry with connecting pads, a patterned diffusion barrier, and a solder mask. The copper circuitry is formed on the core layer. The patterned diffusion barrier has such a pattern identical to the one of the copper circuitry that an upper surface of the copper circuitry is completely covered. The substrate further has a bonding layer formed on a portion of the patterned diffusion barrier inside the solder mask's opening. Therefore, diffusion of copper ions from the copper circuitry of the substrate to the active surface of the chip can be avoided to prevent function failure of the chip.
摘要翻译：揭示了使用铜工艺的芯片的半导体封装。使用铜工艺的芯片设置在基板上。衬底具有芯层，具有连接焊盘的铜电路，图案化扩散阻挡层和焊接掩模。铜电路形成在芯层上。图案化扩散屏障具有与铜电路的上表面完全覆盖的铜电路中的一种相同的图案。衬底还具有形成在焊料掩模的开口内部的图案化扩散阻挡层的一部分上的结合层。因此，可以避免铜离子从衬底的铜电路扩散到芯片的有源表面，以防止芯片的功能故障。

2. 发明授权

US07902666B1 Flip chip device having soldered metal posts by surface mounting 有权
标题翻译：倒装芯片装置通过表面安装焊接金属柱
公开(公告)号：US07902666B1
公开(公告)日：2011-03-08
申请号：US12573608
申请日：2009-10-05
申请人： Hung-Hsin Hsu , Jui-Ching Hsu
发明人： Hung-Hsin Hsu , Jui-Ching Hsu
IPC分类号： H01L23/48
CPC分类号： H01L23/49838 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/0603 , H01L2224/06051 , H01L2224/13013 , H01L2224/13014 , H01L2224/13015 , H01L2224/1308 , H01L2224/13082 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/14051 , H01L2224/14131 , H01L2224/14135 , H01L2224/14177 , H01L2224/14179 , H01L2224/81121 , H01L2224/81136 , H01L2224/81143 , H01L2224/81801 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00014 , H01L2224/13099
摘要： A disclosed semiconductor device having MPS-C2 (Metal Post Solder-Chip Connection) structure can be mounted on a PCB by an SMT mounter. A chip is disposed on a substrate. The substrate has a plurality of connecting pads and a plurality of accessory pads, and the chip has a plurality of corresponding metal posts and a plurality of accessory bumps. The dimensions on the soldered flat tops of the accessory bumps are corresponding to the soldered areas of the accessory pads where each soldered flat top has a plurality of angular corners and an edge between two adjacent angular corners where the length of the edge is twice greater than the pad pitch. Therefore, the displaced or rotational displaced metal posts can be pulled back and self-aligned during reflow processes so that an SMT mounter with poor alignment accuracy can be implemented for flip-chip bonding the semiconductor device having MPS-C2 structure to replace the conventional expensive flip-chip die bonder and to achieve higher productivity. Furthermore, the shape of the flat top surfaces of the metal posts does not have to match with the shape of the connecting pads.
摘要翻译：具有MPS-C2（金属后焊接 - 芯片连接）结构的公开的半导体器件可以通过SMT贴片机安装在PCB上。芯片设置在基板上。基板具有多个连接焊盘和多个附件焊盘，并且该芯片具有多个对应的金属柱和多个附件凸块。附件凸块的焊接平顶上的尺寸对应于附件垫的焊接区域，其中每个焊接平顶具有多个角角和两个相邻角角之间的边缘，其中边缘的长度大于垫间距。因此，可以在回流工艺期间将位移或旋转位移的金属柱拉回并自对准，从而可以实现具有差的对准精度的SMT贴片机用于倒装芯片接合具有MPS-C2结构的半导体器件来代替常规的昂贵倒装芯片焊接机并实现更高的生产率。此外，金属柱的平坦顶面的形状不必与连接垫的形状相匹配。

3. 发明申请

US20110156238A1 SEMICONDUCTOR PACKAGE HAVING CHIP USING COPPER PROCESS 有权
标题翻译：具有使用铜工艺的芯片的半导体封装
公开(公告)号：US20110156238A1
公开(公告)日：2011-06-30
申请号：US12649092
申请日：2009-12-29
申请人： Hung-Hsin Hsu , Chin-Ming Hsu , Jui-Ching Hsu
发明人： Hung-Hsin Hsu , Chin-Ming Hsu , Jui-Ching Hsu
IPC分类号： H01L23/49 , H01L23/498
CPC分类号： H01L24/05 , H01L23/498 , H01L23/49866 , H01L24/27 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/05647 , H01L2224/274 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48145 , H01L2224/48227 , H01L2224/48228 , H01L2224/484 , H01L2224/48644 , H01L2224/48647 , H01L2224/48844 , H01L2224/48847 , H01L2224/73265 , H01L2224/83101 , H01L2224/83856 , H01L2224/85444 , H01L2225/06506 , H01L2225/0651 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2924/00011 , H01L2224/45099
摘要： A semiconductor package having chip using copper process is revealed. A chip using copper process is disposed on a substrate. The substrate has a core layer, a copper circuitry with connecting pads, a patterned diffusion barrier, and a solder mask. The copper circuitry is formed on the core layer. The patterned diffusion barrier has such a pattern identical to the one of the copper circuitry that an upper surface of the copper circuitry is completely covered. The substrate further has a bonding layer formed on a portion of the patterned diffusion barrier inside the solder mask's opening. Therefore, diffusion of copper ions from the copper circuitry of the substrate to the active surface of the chip can be avoided to prevent function failure of the chip.
摘要翻译：揭示了使用铜工艺的芯片的半导体封装。使用铜工艺的芯片设置在基板上。衬底具有芯层，具有连接焊盘的铜电路，图案化扩散阻挡层和焊接掩模。铜电路形成在芯层上。图案化扩散屏障具有与铜电路的上表面完全覆盖的铜电路中的一种相同的图案。衬底还具有形成在焊料掩模的开口内部的图案化扩散阻挡层的一部分上的结合层。因此，可以避免铜离子从衬底的铜电路扩散到芯片的有源表面，以防止芯片的功能故障。

4. 发明申请

US20110133327A1 SEMICONDUCTOR PACKAGE OF METAL POST SOLDER-CHIP CONNECTION 审中-公开
标题翻译：金属焊接芯片连接的半导体封装
公开(公告)号：US20110133327A1
公开(公告)日：2011-06-09
申请号：US12634330
申请日：2009-12-09
申请人： Hung-Hsin Hsu , Chin-Ming Hsu , Jui-Ching Hsu
发明人： Hung-Hsin Hsu , Chin-Ming Hsu , Jui-Ching Hsu
IPC分类号： H01L23/498
CPC分类号： H01L23/498 , H01L21/563 , H01L23/49816 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/01078 , H01L2924/01079 , H01L2924/00
摘要： A semiconductor package with MPS-C2 configuration is revealed, primarily comprising a substrate and a chip. A plurality of leads covered by a solder mask having a rectangular slot disposed on the top surface of the substrate to expose parts of the leads. A plurality of metal pillars are disposed on the active surface of the chip. A patterned plating layer is partially formed on the exposed portions of the leads located inside the slot to form a plurality of plating-defined fingers. Therefore, the soldering area of the solder on the leads can be constrained without exceeding the patterned plating layer to avoid issue of excessive solder ability.
摘要翻译：揭示了具有MPS-C2构型的半导体封装，主要包括衬底和芯片。由焊料掩模覆盖的多个引线，其具有设置在基板的顶表面上以暴露引线部分的矩形槽。多个金属柱设置在芯片的有源表面上。图案化镀层部分地形成在位于槽内的引线的暴露部分上以形成多个电镀限定的指状物。因此，可以限制焊料在引线上的焊接区域而不超过图案化的镀层，以避免发生过度的焊接能力。

5. 发明授权

US07879648B1 Fabrication method for high pin count chip package 失效
标题翻译：高引脚数芯片封装的制造方法
公开(公告)号：US07879648B1
公开(公告)日：2011-02-01
申请号：US12688389
申请日：2010-01-15
申请人： Hsing-Der Chung , Hung-Hsin Hsu
发明人： Hsing-Der Chung , Hung-Hsin Hsu
IPC分类号： H01L21/00
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49541 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A fabrication method for a high pin count chip package is provided herein. First, a lead frame is provided, wherein the lead frame has a chip carrier and a plurality of first lead pins configured around the chip carrier. A first channel is formed on the first lead pins to define a first contact portions and a second contact portion. A die mounting process, a wire bonding process, and a molding process are performed in turn, wherein the molding compound is utilized to encapsulate the chip, the wires, and the first channel. After that, a backside sawing process is performed to electrically isolate the first contact portions and the second contact portions. The present invention achieves high pin count chip package without changing the appearance and size of product and the reasonable width limitation of the lead pins.
摘要翻译：本发明提供了一种高引脚数芯片封装的制造方法。首先，提供引线框，其中引线框具有芯片载体和围绕芯片载体配置的多个第一引线引脚。第一通道形成在第一引脚上以限定第一接触部分和第二接触部分。依次进行模具安装工艺，引线接合工艺和模制工艺，其中模塑料用于封装芯片，导线和第一通道。之后，执行背面锯切工艺以电隔离第一接触部分和第二接触部分。本发明在不改变产品的外观和尺寸以及引脚的合理宽度限制的情况下实现了高引脚数的芯片封装。

6. 发明授权

US08048721B2 Method for filling multi-layer chip-stacked gaps 失效
标题翻译：填充多层芯片堆叠间隙的方法
公开(公告)号：US08048721B2
公开(公告)日：2011-11-01
申请号：US12727033
申请日：2010-03-18
申请人： Hung-Hsin Hsu , Wei-Chih Chien
发明人： Hung-Hsin Hsu , Wei-Chih Chien
IPC分类号： H01L21/00
CPC分类号： H01L21/563 , H01L23/3121 , H01L24/27 , H01L24/743 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/15787 , H01L2924/181 , H01L2924/351 , H01L2924/00
摘要： A method for filling multi-layer chip-stacked gaps is revealed, primarily comprising the steps as below. Firstly, a chip-stacked assembly is provided, comprising a substrate and a plurality of chips vertically stacked on the substrate where at least a first underfilling gap is formed between each two adjacent ones of the stacked chips with a height difference from the substrate. Then, the chip-stacked assembly is flipped and dipped into an underfilling material where the underfilling material is disposed in a storage tank in a flowing state to completely fill the first underfilling gap. Then, the chip-stacked assembly is taken out. Finally, the chip-stacked assembly is heated to cure the underfilling material filled in the first underfilling gap. Accordingly, multi-layer chip-stacked gaps with different heights can be simultaneously filled at one single step. The conventional underfilling difficulty of multi-layer chip-stacked gaps can be solved leading to higher productivity.
摘要翻译：揭示了填充多层芯片堆叠间隙的方法，主要包括以下步骤。首先，提供了一种芯片堆叠组件，其包括衬底和垂直堆叠在衬底上的多个芯片，其中至少第一底部填充间隙形成在每个两个相邻的堆叠芯片之间，与衬底的高度差异。然后，将芯片堆叠的组件翻转并浸入底部填充材料中，其中底部填充材料以流动状态设置在储罐中以完全填充第一未填充间隙。然后，取出芯片堆叠的组件。最后，将芯片堆叠的组件加热以固化填充在第一底部填充间隙中的底部填充材料。因此，可以在一个单一步骤中同时填充具有不同高度的多层芯片堆叠的间隙。可以解决多层芯片堆叠间隙的常规填充难度，从而提高生产率。

7. 发明申请

US20080265389A1 Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications 失效
标题翻译：用于多芯片堆叠的基板，利用基板的多芯片堆叠封装及其应用
公开(公告)号：US20080265389A1
公开(公告)日：2008-10-30
申请号：US11790826
申请日：2007-04-27
申请人： Hung-Hsin Hsu , Chih-Wei Wu
发明人： Hung-Hsin Hsu , Chih-Wei Wu
IPC分类号： H01L23/02
CPC分类号： H01L23/49838 , H01L23/3121 , H01L23/5382 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48195 , H01L2224/48227 , H01L2224/48228 , H01L2224/49113 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2225/06575 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A substrate for multi-chip stacking and a multi-chip stack package utilizing the substrate and its applications are disclosed. The substrate comprises a first wire-bonding finger, a second wire-bonding finger, a trace configured for electrical transmission and a loop wiring on a same surface. The first wire-bonding finger and the second wire-bonding finger are adjacent each other and to a die-attaching area of the substrate. The loop wiring connects the first wire-bonding finger with the second wire-bonding finger in series and connected to the trace. The loop wiring can be selectively broken or not when at least two chips are stacked on the die-attaching area and electrically connected to the first and second wire-bonding fingers respectively. Accordingly, the chips can operate respectively and independently without mutual interference if one of the chips is fail. Moreover, there is merit to apply the multi-chip stack package utilizing the substrate because it can be repaired after molding and without removing any bonding wire during semiconductor packaging processes.
摘要翻译：公开了一种用于多芯片堆叠的基板和利用该基板及其应用的多芯片堆叠封装。基板包括第一引线接合指状物，第二引线键合指状物，构造成用于电传输的迹线和在同一表面上的环形布线。第一引线接合指和第二引线接合指彼此相邻并且与基板的管芯附接区相邻。环路布线将第一引线接合指状物与第二引线键合指针串联连接并连接至迹线。当至少两个芯片堆叠在芯片安装区域上并且分别电连接到第一和第二引线键合手指时，环路布线可以选择性地断开。因此，如果其中一个芯片发生故障，则芯片可以分别且独立地操作而没有相互干扰。此外，由于可以在模制之后修复并且在半导体封装工艺期间不去除任何接合线，所以应用使用基板的多芯片堆叠封装是有价值的。

8. 发明申请

US20080203553A1 Stackable bare-die package 审中-公开
标题翻译：可堆叠的裸片封装
公开(公告)号：US20080203553A1
公开(公告)日：2008-08-28
申请号：US11709893
申请日：2007-02-23
申请人： Hung-Hsin Hsu , Hwe-Zhong Chen
发明人： Hung-Hsin Hsu , Hwe-Zhong Chen
IPC分类号： H01L23/02
CPC分类号： H01L23/13 , H01L23/3128 , H01L24/48 , H01L25/105 , H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stackable bare-die package primarily comprises a substrate, a chip, a plurality of bonding wires and an encapsulant. The substrate has a slot where a step is formed inside the slot where a plurality of inner fingers are disposed on the step. A plurality of outer pads are disposed on the bottom surface and a plurality of transfer pads on the top surface. The chip is disposed on the top surface and is electrically connected to the inner fingers by a plurality of bonding wires passing through the slot. An encapsulant is formed inside the slot to encapsulate the bonding wires. There is a height difference between the step and the bottom surface so that the loop height of the bonding wires will not exceed the bottom surface. Therefore, when stacking the stackable bare-die packages, the exposed back surface of the chip will not be touched nor stressed to avoid die crack issues.
摘要翻译：可堆叠裸裸片封装主要包括衬底，芯片，多个接合线和密封剂。基板具有狭槽，在台阶上设置有多个内指的槽内形成有台阶。多个外垫设置在底表面上，并且在顶表面上设置多个转移垫。芯片设置在顶表面上，并且通过穿过槽的多个接合线电连接到内指。在狭槽内形成密封剂以封装接合线。台阶和底面之间存在高度差，使得接合线的环高不会超过底面。因此，当堆叠可堆叠的裸芯片封装时，芯片的裸露背面将不会被触摸，也不会受到压力以避免模具裂纹问题。

9. 发明授权

US08237273B2 Metal post chip connecting device and method free to use soldering material 有权
标题翻译：金属后片连接装置和方法可自由使用焊接材料
公开(公告)号：US08237273B2
公开(公告)日：2012-08-07
申请号：US12717591
申请日：2010-03-04
申请人： Hung-Hsin Hsu , Chih-Ming Ko
发明人： Hung-Hsin Hsu , Chih-Ming Ko
IPC分类号： H01L23/498
CPC分类号： H01L23/498 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
摘要： A metal post chip connecting device without soldering materials is revealed, primarily comprising a chip and a substrate. A plurality of metal pillars are disposed on and extruded from a surface of the chip where each metal pillar has an end surface and two corresponding parallel sidewalls. The substrate has an upper surface and a plurality of bonding pads disposed on the upper surface where each bonding pad has a concaved bottom surface and two corresponding concaved sidewalls. The chip is bonded onto the upper surface of the substrate through heat, pressure, and ultrasonic power so that the end surfaces of the metal pillars self-solder to the concaved bottom surfaces and two parallel sidewalls of the metal pillars partially self-solder to two concaved sidewalls to form U-shape cross-sections of metal bonding between the metal pillars and the bonding pads. Therefore, there is no need for the conventional solder paste as chip connection to increase conductivity of the soldering points, especially, to save the soldering cost for MPS-C2 products and to greatly enhance the bonding strength of the soldering points. The manufacturing method of the above described metal post chip connecting device is also revealed.
摘要翻译：揭示了没有焊接材料的金属后片连接装置，主要包括芯片和基板。多个金属柱设置在每个金属柱具有端面和两个对应的平行侧壁的芯片的表面上并从其挤出。衬底具有上表面和设置在上表面上的多个焊盘，其中每个焊盘具有凹面底面和两个相应的凹面侧壁。芯片通过热，压力和超声功率结合到基板的上表面上，使得金属柱的端面自身焊接到凹陷的底面，金属柱的两个平行的侧壁部分自焊到两个凹形侧壁形成在金属柱和接合垫之间的金属结合的U形横截面。因此，不需要将传统的焊膏作为芯片连接来提高焊接点的导电性，特别是为了节省MPS-C2产品的焊接成本，并大大提高焊接点的焊接强度。还揭示了上述金属后片连接装置的制造方法。

10. 发明授权

US08115319B2 Flip chip package maintaining alignment during soldering 失效
标题翻译：翻转芯片封装在焊接期间保持对准
公开(公告)号：US08115319B2
公开(公告)日：2012-02-14
申请号：US12717518
申请日：2010-03-04
申请人： Hung-Hsin Hsu , Chih-Ming Ko
发明人： Hung-Hsin Hsu , Chih-Ming Ko
IPC分类号： H01L23/498
CPC分类号： H01L23/544 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/81141 , H01L2224/81191 , H01L2924/14 , H01L2924/00
摘要： Disclosed is a flip chip package maintaining alignment during soldering, primarily comprising a chip and a substrate. A plurality of bumps and at least an extruded alignment key are disposed on the active surface of the chip. The substrate has a plurality of bonding pads and at least an alignment base where the alignment base has a concaved alignment pattern corresponding to the extruded alignment key. When the chip is disposed on the substrate, the extruded alignment key is embedded into the concaved alignment pattern to achieve accurately align the bumps to the corresponding bonding pads. Therefore, even with the mechanical misalignment due to the accuracy of flip-chip die bonders and the transportation during reflow processes, the bumps of a chip still can accurately align to the bonding pads of the substrate to achieve accurate soldering which is especially beneficial to the mass production of MPS-C2 products.
摘要翻译：公开了一种在焊接期间保持对准的倒装芯片封装，主要包括芯片和基板。在芯片的有效表面上设置有多个凸块和至少一个挤压对准键。基板具有多个接合焊盘和至少一个对准基座，其中对准基座具有对应于挤压对准键的凹入对准图案。当芯片设置在基板上时，将挤出的对准键嵌入到凹形对准图案中，以实现将凸块精确对准到相应的焊盘。因此，即使由于倒装芯片接合器的精度和回流工艺中的输送而导致的机械偏移，芯片的凸块仍能够精确地对准衬底的焊盘，以实现精确的焊接，这对于批量生产MPS-C2产品。

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