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1. 发明授权

US06972994B2 Circuit and a method to screen for defects in an addressable line in a non-volatile memory 有权
标题翻译：电路和一种在非易失性存储器中筛选可寻址线路中的缺陷的方法
公开(公告)号：US06972994B2
公开(公告)日：2005-12-06
申请号：US10797156
申请日：2004-03-09
申请人： Hung Q. Nguyen , Steve Choi , Loc Hoang , Alexander Kotov
发明人： Hung Q. Nguyen , Steve Choi , Loc Hoang , Alexander Kotov
IPC分类号： G11C15/00 , G11C16/06 , G11C29/00
CPC分类号： G11C29/024
摘要： A circuit to screen for defects in an addressable line in a non-volatile memory array comprises a current mirror circuit which has a plurality of mirroring stages. The current mirror circuit is connected to the addressable line and receives a control signal and mirrors the control signal to provide a current to the addressable line. In a preferred embodiment, the current mirror circuit provides a high voltage current to the addressable line which is used to effectuate an operation such as program or erase to the memory cells connected to the addressable line. The change in state or the absence of change in state of the memory cells connected to the addressable line can be used to screen for defects in the addressable line.
摘要翻译：用于屏蔽非易失性存储器阵列中可寻址线路中的缺陷的电路包括具有多个镜像级的电流镜电路。电流镜电路连接到可寻址线路并接收控制信号并镜像控制信号以向可寻址线路提供电流。在优选实施例中，电流镜电路向可寻址线路提供高电压电流，该可寻址线路用于对连接到可寻址线路的存储器单元实现诸如编程或擦除的操作。连接到可寻址线路的存储器单元的状态变化或不存在状态的变化可用于筛选可寻址线路中的缺陷。

2. 发明申请

US20050201152A1 CIRCUIT AND A METHOD TO SCREEN FOR DEFECTS IN AN ADDRESSABLE LINE IN A NON-VOLATILE MEMORY 有权
标题翻译：电路和非易失性存储器中可寻址线路中缺陷的屏蔽方法
公开(公告)号：US20050201152A1
公开(公告)日：2005-09-15
申请号：US10797156
申请日：2004-03-09
申请人： Hung Nguyen , Steve Choi , Loc Hoang , Alexander Kotov
发明人： Hung Nguyen , Steve Choi , Loc Hoang , Alexander Kotov
IPC分类号： G11C15/00 , G11C16/06 , G11C29/00
CPC分类号： G11C29/024
摘要： A circuit to screen for defects in an addressable line in a non-volatile memory array comprises a current mirror circuit which has a plurality of mirroring stages. The current mirror circuit is connected to the addressable line and receives a control signal and mirrors the control signal to provide a current to the addressable line. In a preferred embodiment, the current mirror circuit provides a high voltage current to the addressable line which is used to effectuate an operation such as program or erase to the memory cells connected to the addressable line. The change in state or the absence of change in state of the memory cells connected to the addressable line can be used to screen for defects in the addressable line.
摘要翻译：用于屏蔽非易失性存储器阵列中可寻址线路中的缺陷的电路包括具有多个镜像级的电流镜电路。电流镜电路连接到可寻址线路并接收控制信号并镜像控制信号以向可寻址线路提供电流。在优选实施例中，电流镜电路向可寻址线路提供高电压电流，该可寻址线路用于对连接到可寻址线路的存储器单元实现诸如编程或擦除的操作。连接到可寻址线路的存储器单元的状态变化或不存在状态的变化可用于筛选可寻址线路中的缺陷。

3. 发明申请

US20070070703A1 Flash memory array system including a top gate memory cell 有权
公开(公告)号：US20070070703A1
公开(公告)日：2007-03-29
申请号：US11235901
申请日：2005-09-26
申请人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
发明人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

4. 发明申请

US20070147131A1 Flash memory array system including a top gate memory cell 有权
公开(公告)号：US20070147131A1
公开(公告)日：2007-06-28
申请号：US11707341
申请日：2007-02-16
申请人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
发明人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

5. 发明申请

US20070147111A1 Flash memory array system including a top gate memory cell 有权
标题翻译：包括顶栅存储单元的闪存阵列系统
公开(公告)号：US20070147111A1
公开(公告)日：2007-06-28
申请号：US11707343
申请日：2007-02-16
申请人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
发明人： Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

6. 发明申请

US20060123280A1 Test circuit and method for multilevel cell flash memory 有权
公开(公告)号：US20060123280A1
公开(公告)日：2006-06-08
申请号：US10991702
申请日：2004-11-17
申请人： Hieu Tran , Anh Ly , Sang Nguyen , Vishal Sarin , Hung Nguyen , William Saiki , Loc Hoang
发明人： Hieu Tran , Anh Ly , Sang Nguyen , Vishal Sarin , Hung Nguyen , William Saiki , Loc Hoang
IPC分类号： G11C29/00
CPC分类号： G11C11/5621 , G11C16/04 , G11C29/50 , G11C29/50004
摘要： A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

7. 发明申请

US20060243937A1 HYDRAULIC OVERRIDE 有权
标题翻译：液压油
公开(公告)号：US20060243937A1
公开(公告)日：2006-11-02
申请号：US10908166
申请日：2005-04-29
申请人： Loc Hoang
发明人： Loc Hoang
IPC分类号： F16K31/00
CPC分类号： F16K3/0254 , E21B34/04 , F16K31/04 , F16K31/1221 , F16K31/124
摘要： A valve system comprising a closure member that is linearly translatable within a valve body. A hydraulic override assembly comprises a first end that is connected to the valve body and a first rod member that is connected to the closure member. A linear actuator is connected to a second end of the hydraulic override assembly and comprises a second rod member that is operable to move the first rod member.
摘要翻译：一种阀系统，包括可在阀体内线性平移的封闭构件。液压超越组件包括连接到阀体的第一端和连接到闭合构件的第一杆构件。线性致动器连接到液压超越组件的第二端，并且包括可操作以移动第一杆构件的第二杆构件。

8. 发明申请

US20100176327A1 GATE-COATING PROCESS 有权
标题翻译：浇注过程
公开(公告)号：US20100176327A1
公开(公告)日：2010-07-15
申请号：US12602610
申请日：2008-04-23
申请人： Loc Hoang
发明人： Loc Hoang
IPC分类号： F16K3/02 , B05D3/12 , C23C4/12
CPC分类号： F16K3/0263 , C23C4/01 , C23C4/10 , Y10T29/49281 , Y10T29/49982
摘要： An apparatus that includes a body of a gate configured to seal a gate valve. In certain embodiments, the body has a first face with a first coating disposed thereon, and a second face opposite the first face and having a second coating disposed thereon. The body also may include a flow bore that extends from the first face, through the body of the gate, to the second face and a reference structure that does not have either the first coating or the second coating disposed thereon. In some embodiments, the reference structure is configured to define a plane on the first face, the second face, or both during a planarization process.
摘要翻译：一种装置，其包括构造成密封闸阀的门的主体。在某些实施例中，主体具有设置在其上的第一涂层的第一面和与第一面相对的第二面，其上设置有第二涂层。主体还可以包括从第一面延伸穿过门的主体到第二面的流动孔，以及不具有设置在其上的第一涂层或第二涂层的参考结构。在一些实施例中，参考结构被配置为在平坦化处理期间在第一面，第二面或两者上限定平面。

9. 发明申请

US20060202668A1 Fast voltage regulators for charge pumps 有权
公开(公告)号：US20060202668A1
公开(公告)日：2006-09-14
申请号：US11080070
申请日：2005-03-14
申请人： Hieu Tran , Sang Nguyen , Anh Ly , Hung Nguyen , Wingfu Lau , Nasrin Jaffari , Thuan Vu , Vishal Sarin , Loc Hoang
发明人： Hieu Tran , Sang Nguyen , Anh Ly , Hung Nguyen , Wingfu Lau , Nasrin Jaffari , Thuan Vu , Vishal Sarin , Loc Hoang
IPC分类号： G05F5/00 , G05F1/00
CPC分类号： H02M3/07 , G11C5/145 , H02M1/36 , H02M1/44 , Y10T307/50
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

10. 发明申请

US20060243936A1 MECHANICAL OVERRIDE 有权
标题翻译：机械装置
公开(公告)号：US20060243936A1
公开(公告)日：2006-11-02
申请号：US10908165
申请日：2005-04-29
申请人： Loc Hoang
发明人： Loc Hoang
IPC分类号： F16K31/00
CPC分类号： F16K31/05 , E21B34/04 , F16K3/0254
摘要： A valve system comprising a closure member that is linearly translatable within a valve body. A fail safe assembly is connected to the valve body and a first rod member that is connected to the closure member. A linear actuator is movably connected to the fail safe assembly and is operable to move the first rod member. A mechanical override system is connected to the linear actuator and is operable to move the linear actuator relative to the valve body.
摘要翻译：一种阀系统，包括可在阀体内线性平移的封闭构件。故障安全组件连接到阀体和连接到闭合构件的第一杆构件。线性致动器可移动地连接到故障保护组件，并且可操作以移动第一杆构件。机械超控系统连接到线性致动器并且可操作以相对于阀体移动线性致动器。

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