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    • 8. 发明授权
    • Method for monitoring an internal control signal of a memory device and apparatus therefor
    • 用于监视存储器件的内部控制信号的方法及其装置
    • US07702967B2
    • 2010-04-20
    • US12243292
    • 2008-10-01
    • Ji Hyun KimYoung Jun Nam
    • Ji Hyun KimYoung Jun Nam
    • G11B20/20
    • G11C29/1201G11C29/48
    • Disclosed is a method for monitoring an internal control signal of a memory device and an apparatus therefore. The method includes (a) generating a first signal having a first pulse width by a burst operation command, (b) receiving the first signal, and generating N−1 (where, N is a burst length) second signals having a second pulse width, (c) receiving the first signal and the second signals, and outputting a third signal by changing the first pulse width of the first signal and the second pulse width of the second signals in accordance with a variation of a frequency of a clock signal of the memory device, (d) outputting the third signal to an external pin of the memory device and monitoring the third signal, and (e) adjusting a pulse width of a signal that controls an operation of a data bus connecting a bit-line sense amplifier and a data sense amplifier using the third signal.
    • 公开了一种用于监视存储装置的内部控制信号的方法及装置。 该方法包括:(a)通过脉冲串操作命令产生具有第一脉冲宽度的第一信号,(b)接收第一信号,并产生N-1(其中,N是脉冲串长度)具有第二脉冲宽度的第二信号 ,(c)接收第一信号和第二信号,并且通过根据第一信号的第一脉冲宽度和第二信号的第二脉冲宽度,根据时钟信号的频率的变化来输出第三信号 存储器件,(d)将第三信号输出到存储器件的外部引脚并监视第三信号,以及(e)调节控制连接位线检测的数据总线的操作的信号的脉冲宽度 放大器和使用第三信号的数据读出放大器。
    • 10. 发明授权
    • Apparatus and method for controlling enable time of signal controlling operation of data buses of memory device
    • 用于控制存储器件的数据总线的信号控制操作时间的装置和方法
    • US07177228B2
    • 2007-02-13
    • US10876915
    • 2004-06-25
    • Ji Hyun KimYoung Jun Nam
    • Ji Hyun KimYoung Jun Nam
    • G11C8/00
    • G11C7/1072G11C7/222G11C29/028G11C29/50012G11C2207/2254
    • Disclosed is an apparatus for controlling an enable interval of a signal controlling an operation of data buses which connect a bit line sense amplifier with a data sense amplifier according to a variation of an operational frequency of a memory device. The apparatus comprises a pulse width control section for changing the pulse width of an input signal depending on the operational frequency of the memory device after receiving the input signal, a signal transmission section for buffering a signal outputted from the pulse width control section, and an output section for receiving a signal outputted from the signal transmission section so as to output a first signal for controlling the signal to control the operation of the data buses.
    • 公开了一种用于控制控制数据总线的操作的信号的使能间隔的装置,该数据总线根据存储器件的工作频率的变化将位线读出放大器与数据读出​​放大器连接起来。 该装置包括:脉冲宽度控制部分,用于在接收到输入信号之后根据存储器件的工作频率改变输入信号的脉冲宽度;信号传输部分,用于缓冲从脉冲宽度控制部分输出的信号;以及 输出部分,用于接收从信号传输部分输出的信号,以输出用于控制信号的第一信号,以控制数据总线的操作。