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1. 发明申请

US20080001213A1 STRUCTURES AND METHODS FOR MANUFACTURING HIGH DENSITY NARROW WIDTH MOSFETS 审中-公开
标题翻译：用于制造高密度纳米宽度MOSFET的结构和方法
公开(公告)号：US20080001213A1
公开(公告)日：2008-01-03
申请号：US11427405
申请日：2006-06-29
申请人： Huilong Zhu , Byeong Y. Kim , Effendi Leobandung
发明人： Huilong Zhu , Byeong Y. Kim , Effendi Leobandung
IPC分类号： H01L29/76
CPC分类号： H01L21/823878 , H01L21/76264 , H01L21/823814 , H01L21/82385 , H01L29/78696
摘要： Reverse narrow width effects are provided consistent with reduced spacing between field effect transistors by an impurity or dopant implantation perpendicular to a semiconductor substrate through gaps formed by selective removal of a layer of material deposited to a selected thickness rather than implantation at an angle in accordance with a patterned resist resulting in superior accuracy, controllability and repeatability of the location of the implanted region and avoidance of implantation at undesired locations. A multi-layer structure having at least three component materials which can be removed selectively to each other is preferred for forming the gaps for confining the implantation preferably performed through a layer of one of the component materials which also functions as an etch stop.
摘要翻译：提供反向窄宽度效应与场效应晶体管之间的间隔减小，通过垂直于半导体衬底的杂质或掺杂剂注入，通过选择性去除沉积到所选厚度的材料层而形成的间隙，而不是按照图案化的抗蚀剂导致注入区域的位置的优良精度，可控性和重复性以及避免植入在不期望的位置。具有至少可以选择性地彼此移除的三种组分材料的多层结构优选用于形成用于限制注入的间隙，优选通过也用作蚀刻停止层的一种组分材料的层进行。

2. 发明授权

US07592245B2 Poly filled substrate contact on SOI structure 失效
标题翻译：多晶硅填充衬底接触SOI结构
公开(公告)号：US07592245B2
公开(公告)日：2009-09-22
申请号：US12014127
申请日：2008-01-15
申请人： David M. Dobuzinsky , Byeong Y. Kim , Effendi Leobandung , Munir D. Naeem , Brian L. Tessier
发明人： David M. Dobuzinsky , Byeong Y. Kim , Effendi Leobandung , Munir D. Naeem , Brian L. Tessier
IPC分类号： H01L21/44
CPC分类号： H01L21/84
摘要： Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.
摘要翻译：本文的实施方案提供了一种用于在SOI结构上形成多孔填充衬底接触的方法。该方法在衬底上形成绝缘体，并在绝缘体内形成衬底接触孔。绝缘子表面水平高于最终结构。接下来，执行聚过填料，包括用多晶硅填充衬底接触孔并用多晶硅覆盖绝缘体。具体地，多晶硅的厚度大于基板接触孔的尺寸。接下来，蚀刻多晶硅，其中去除多晶硅的一部分，并且其中衬底接触孔部分地被多晶硅填充。此外，多晶硅的蚀刻在多晶硅的顶部内形成凹形凹部。所述多晶硅的蚀刻不与衬底接触。绝缘体的过剩被抛光到所需的水平。

3. 发明授权

US07358172B2 Poly filled substrate contact on SOI structure 有权
标题翻译：多晶硅填充衬底接触SOI结构
公开(公告)号：US07358172B2
公开(公告)日：2008-04-15
申请号：US11307762
申请日：2006-02-21
申请人： David M. Dobuzinsky , Byeong Y. Kim , Effendi Leobandung , Munir D. Naeem , Brian L. Tessier
发明人： David M. Dobuzinsky , Byeong Y. Kim , Effendi Leobandung , Munir D. Naeem , Brian L. Tessier
IPC分类号： H01L21/44
CPC分类号： H01L21/84
摘要： Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.
摘要翻译：本文的实施方案提供了一种用于在SOI结构上形成多孔填充衬底接触的方法。该方法在衬底上形成绝缘体，并在绝缘体内形成衬底接触孔。绝缘子表面水平高于最终结构。接下来，执行聚过填料，包括用多晶硅填充衬底接触孔并用多晶硅覆盖绝缘体。具体地，多晶硅的厚度大于基板接触孔的尺寸。接下来，蚀刻多晶硅，其中去除多晶硅的一部分，并且其中衬底接触孔部分地被多晶硅填充。此外，多晶硅的蚀刻在多晶硅的顶部内形成凹形凹部。所述多晶硅的蚀刻不与衬底接触。绝缘体的过剩被抛光到所需的水平。

4. 发明授权

US08629017B2 Structure and method to form EDRAM on SOI substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US08629017B2
公开(公告)日：2014-01-14
申请号：US13417900
申请日：2012-03-12
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

5. 发明授权

US08188528B2 Structure and method to form EDRAM on SOI substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US08188528B2
公开(公告)日：2012-05-29
申请号：US12437242
申请日：2009-05-07
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

6. 发明申请

US20120171827A1 STRUCTURE AND METHOD TO FORM EDRAM ON SOI SUBSTRATE 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US20120171827A1
公开(公告)日：2012-07-05
申请号：US13417900
申请日：2012-03-12
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

7. 发明授权

US07790581B2 Semiconductor substrate with multiple crystallographic orientations 有权
标题翻译：具有多个晶体取向的半导体衬底
公开(公告)号：US07790581B2
公开(公告)日：2010-09-07
申请号：US11306713
申请日：2006-01-09
申请人： Byeong Y. Kim , Xiaomeng Chen , Woo-Hyeong Lee , Huilong Zhu
发明人： Byeong Y. Kim , Xiaomeng Chen , Woo-Hyeong Lee , Huilong Zhu
IPC分类号： H01L21/20 , H01L21/36 , H01L21/00
CPC分类号： H01L29/1083 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/045 , H01L29/0649 , H01L29/78 , H01L29/7848 , H01L29/7849 , H01L29/78603 , H01L29/78654 , H01L29/78687
摘要： A pair of semiconductor structures and a method for fabricating a semiconductor structure each utilize a semiconductor substrate having a first crystallographic orientation, and a dielectric layer located thereupon. The method provides for epitaxially growing a semiconductor layer on the semiconductor substrate to encapsulate the dielectric layer. The method also provides for patterning the semiconductor layer to yield a semiconductor structure that comprises a bulk semiconductor structure and a semiconductor-on-insulator structure, or alternatively a patterned semiconductor layer that straddles the dielectric layer and contacts the semiconductor substrate.
摘要翻译：一对半导体结构和半导体结构的制造方法各自使用具有第一晶体取向的半导体衬底和位于其上的电介质层。该方法提供了在半导体衬底上外延生长半导体层以封装介电层。该方法还提供了图案化半导体层以产生包括体半导体结构和绝缘体上半导体结构的半导体结构，或者替代地跨越电介质层并接触半导体衬底的图案化半导体层。

8. 发明申请

US20100283093A1 Structure and Method to Form EDRAM on SOI Substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US20100283093A1
公开(公告)日：2010-11-11
申请号：US12437242
申请日：2009-05-07
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L27/10 , H01L21/02
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

9. 发明申请

US20080185592A1 SEMICONDUCTOR SUBSTRATE WITH MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS 有权
标题翻译：具有多个晶体取向的半导体衬底
公开(公告)号：US20080185592A1
公开(公告)日：2008-08-07
申请号：US11306713
申请日：2006-01-09
申请人： Byeong Y. Kim , Xiaomeng Chen , Woo-Hyeong Lee , Huilong Zhu
发明人： Byeong Y. Kim , Xiaomeng Chen , Woo-Hyeong Lee , Huilong Zhu
IPC分类号： H01L29/04 , H01L21/20
CPC分类号： H01L29/1083 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/045 , H01L29/0649 , H01L29/78 , H01L29/7848 , H01L29/7849 , H01L29/78603 , H01L29/78654 , H01L29/78687
摘要： A pair of semiconductor structures and a method for fabricating a semiconductor structure each utilize a semiconductor substrate having a first crystallographic orientation, and a dielectric layer located thereupon. The method provides for epitaxially growing a semiconductor layer on the semiconductor substrate to encapsulate the dielectric layer. The method also provides for patterning the semiconductor layer to yield a semiconductor structure that comprises a bulk semiconductor structure and a semiconductor-on-insulator structure, or alternatively a patterned semiconductor layer that straddles the dielectric layer and contacts the semiconductor substrate.
摘要翻译：一对半导体结构和半导体结构的制造方法各自使用具有第一晶体取向的半导体衬底和位于其上的电介质层。该方法提供了在半导体衬底上外延生长半导体层以封装介电层。该方法还提供了图案化半导体层以产生包括体半导体结构和绝缘体上半导体结构的半导体结构，或者替代地跨越电介质层并接触半导体衬底的图案化半导体层。

10. 发明授权

US08679938B2 Shallow trench isolation for device including deep trench capacitors 失效
标题翻译：用于包括深沟槽电容器的器件的浅沟槽隔离
公开(公告)号：US08679938B2
公开(公告)日：2014-03-25
申请号：US13366576
申请日：2012-02-06
申请人： Sunfei Fang , Oleg Gluschenkov , Byeong Y. Kim , Rishikesh Krishnan , Daewon Yang
发明人： Sunfei Fang , Oleg Gluschenkov , Byeong Y. Kim , Rishikesh Krishnan , Daewon Yang
IPC分类号： H01L21/20
CPC分类号： H01L27/10861 , H01L21/76224 , H01L29/66181 , H01L29/945
摘要： A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less.
摘要翻译：在包括沟槽电容元件的器件的有源区中形成浅沟槽隔离（STI）的方法，包括金属板和高k电介质的沟槽电容元件包括在器件的有源区中蚀刻STI沟槽，其中所述STI沟槽直接邻近所述沟槽电容元件的金属板或高k电介质中的至少一个; 以及在所述STI沟槽中形成氧化物衬垫，其中所述氧化物衬垫选择性地形成到所述金属板或高k电介质，其中形成所述氧化物衬垫在约600℃或更低的温度下进行。

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