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1. 发明授权

US06294435B1 Method of reducing word line resistance and contact resistance 有权
标题翻译：降低字线电阻和接触电阻的方法
公开(公告)号：US06294435B1
公开(公告)日：2001-09-25
申请号：US09414804
申请日：1999-10-08
申请人： Huey-Chi Chu , Jia-Ching Doong , Chung-Pin Yang
发明人： Huey-Chi Chu , Jia-Ching Doong , Chung-Pin Yang
IPC分类号： H01L213215
CPC分类号： H01L21/28061
摘要： By introducing a carefully controlled anneal step after the deposition of tungsten silicide (onto a layer of polysilicon) but before the deposition of a layer of silicon oxide, interaction between the tungsten silicide and a subsequently deposited layer of silicon oxide is greatly reduced or eliminated. This gives good values for the resistance of gate lines formed from the composite as well as for the contact resistance between the polysilicon and the tungsten silicide.
摘要翻译：通过在沉积硅化钨（在多晶硅层上）之后但在沉积氧化硅层之前引入精心控制的退火步骤，硅化硅与随后沉积的氧化硅层之间的相互作用被大大减少或消除。这为由复合材料形成的栅极线的电阻以及多晶硅和硅化钨之间的接触电阻提供了良好的值。

2. 发明授权

US06833578B1 Method and structure improving isolation between memory cell passing gate and capacitor 有权
标题翻译：存储单元通过栅极和电容器之间的隔离方法和结构
公开(公告)号：US06833578B1
公开(公告)日：2004-12-21
申请号：US10733216
申请日：2003-12-11
申请人： Kuo-Chi Tu , Chun-Yao Chen , Huey-Chi Chu , Chung-Wei Chang , Tien-Lu Lin , Kuo-Ching Huang , Wen-Cheng Chen , Tsung-Hsun Huang , Hsiao-Hui Tseng
发明人： Kuo-Chi Tu , Chun-Yao Chen , Huey-Chi Chu , Chung-Wei Chang , Tien-Lu Lin , Kuo-Ching Huang , Wen-Cheng Chen , Tsung-Hsun Huang , Hsiao-Hui Tseng
IPC分类号： H01L27108
CPC分类号： H01L28/57 , H01L27/11 , H01L28/90
摘要： A memory cell comprising a capacitor having a dielectric layer interposing first and second vertically disposed electrodes, an insulating lining located over the capacitor, and a transistor gate extension passing over the capacitor. A spacer isolates an end of one of the capacitor electrodes from the transistor gate extension. In one embodiment, the spacer includes a first non-planar profile configured to engage a second non-planar profile comprising ends of the one of the capacitor electrodes and the insulating lining.
摘要翻译：一种存储单元，包括具有插入第一和第二垂直设置的电极的介电层的电容器，位于电容器上方的绝缘衬垫，以及通过电容器的晶体管栅极延伸。间隔件将电容器电极之一的端部与晶体管栅极延伸部隔离。在一个实施例中，间隔件包括构造成接合包括电容器电极之一和绝缘衬里的端部的第二非平面轮廓的第一非平面轮廓。

3. 发明申请

US20140042590A1 Metal-Insulator-Metal Capacitor and Method of Fabricating 有权
标题翻译：金属绝缘体 - 金属电容器和制造方法
公开(公告)号：US20140042590A1
公开(公告)日：2014-02-13
申请号：US13571441
申请日：2012-08-10
申请人： Kuo-Ji Chen , Wen-Chuan Chiang , Huey-Chi Chu , Ming-Hsiang Song , Chen-Jong Wang
发明人： Kuo-Ji Chen , Wen-Chuan Chiang , Huey-Chi Chu , Ming-Hsiang Song , Chen-Jong Wang
IPC分类号： H01L29/92
CPC分类号： H01L28/60 , H01L28/75 , H01L29/92
摘要： Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.
摘要翻译：公开了用于制造金属 - 绝缘体 - 金属（MIM）电容器的方法和装置。 MIM电容器可以包括电极，其可以是具有瓶颈的顶部或底部电极。 MIM电容器可以包括与通孔的侧壁接触的电极，其可以是顶部或底部电极。当泄漏电流超过规格时，电极的侧壁接触或瓶颈可燃烧形成高阻抗路径，而电极的侧壁接触或瓶颈对于正常的MIM操作没有影响。 MIM电容器可用作去耦电容器。

4. 发明授权

US06720232B1 Method of fabricating an embedded DRAM for metal-insulator-metal (MIM) capacitor structure 有权
标题翻译：制造金属 - 绝缘体 - 金属（MIM）电容器结构的嵌入式DRAM的方法
公开(公告)号：US06720232B1
公开(公告)日：2004-04-13
申请号：US10411347
申请日：2003-04-10
申请人： Kuo-Chi Tu , Chun-Yao Chen , Huey-Chi Chu
发明人： Kuo-Chi Tu , Chun-Yao Chen , Huey-Chi Chu
IPC分类号： H01L2120
CPC分类号： H01L27/10852 , H01L27/10811 , H01L27/10894 , H01L27/10897 , H01L28/91
摘要： A method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is described. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the substrate and in a memory area of the substrate and providing node contact plugs to node contact regions within the substrate in the memory area. Thereafter, capacitors are fabricated in a twisted trench in a self-aligned copper process.
摘要翻译：描述了在嵌入式DRAM工艺中制造金属 - 绝缘体 - 金属电容器的方法。多个接触插塞通过绝缘层提供到衬底中的半导体器件结构，其中接触插塞形成在衬底的逻辑区域中并且在衬底的存储区域中并且将节点接触插塞提供到衬底内的节点接触区域底物在记忆区。此后，电容器在自对准铜工艺中以扭曲的沟槽制造。

5. 发明授权

US06309968B1 Method to improve intrinsic refresh time and dichlorosilane formed gate oxide reliability 有权
标题翻译：提高固化刷新时间和二氯硅烷形成栅极氧化可靠性的方法
公开(公告)号：US06309968B1
公开(公告)日：2001-10-30
申请号：US09391887
申请日：1999-09-07
申请人： Huey-Chi Chu , Yeh-Sen Lin
发明人： Huey-Chi Chu , Yeh-Sen Lin
IPC分类号： H01L2144
CPC分类号： H01L21/324 , H01L21/28176 , H01L21/28518 , H01L21/3003
摘要： The intrinsic refresh time of a DRAM and the reliability of the gate oxide of the pass transistor of the memory cell of the DRAM is improved by a method to form electronic components of an integrated circuit on a semiconductor substrate that will eliminate damage to molecular bonds and reduce junction leakage within the semiconductor substrate. The method begins by forming said electronic components using recognized methods to create implantations, insulating oxide layers, selectively etching the insulating oxide layers and deposited conductive layers to assemble the transistors and capacitors of the integrated circuit. Interconnections between the electronic components are then formed. The interconnections include multiple layers of metal, multiple layers of heavily doped polycrystalline silicon, and silicon/metal alloys to connect terminals of said electronic components to the multiple layers of metals and multiple layers of heavily doped polycrystalline silicon. The molecular bonds are then repaired by sintering the semiconductor substrate in an atmosphere of atomic hydrogen (H2) for a time and a temperature sufficient to repair damage to the molecular bonds within said semiconductor substrate so as to reduce said junction leakage of said transistors and to remove traps between the surface of the semiconductor substrate and the gate oxide of the transistors.
摘要翻译：通过在半导体衬底上形成集成电路的电子部件的方法来改善DRAM的固有刷新时间和DRAM的存储单元的通过晶体管的栅极氧化物的可靠性，该方法将消除对分子键的损害，减少半导体衬底内的结漏电。该方法开始于通过使用识别的方法形成所述电子部件以产生注入，绝缘氧化物层，选择性地蚀刻绝缘氧化物层和沉积的导电层以组装集成电路的晶体管和电容器。然后形成电子部件之间的互连。互连包括多层金属，多层重掺杂多晶硅以及硅/金属合金，以将所述电子部件的端子连接到多层金属和多层重掺杂多晶硅。然后通过在原子氢气（H2）的气氛中烧结半导体衬底一段时间和足以修复对所述半导体衬底内的分子键的损伤的温度来修复分子键，以减少所述晶体管的所述结漏电，并且去除半导体衬底的表面和晶体管的栅极氧化物之间的阱。

6. 发明授权

US09178008B2 Metal-insulator-metal capacitor with current leakage protection 有权
标题翻译：金属绝缘金属电容器，具有漏电保护
公开(公告)号：US09178008B2
公开(公告)日：2015-11-03
申请号：US13571441
申请日：2012-08-10
申请人： Kuo-Ji Chen , Wen-Chuan Chiang , Huey-Chi Chu , Ming-Hsiang Song , Chen-Jong Wang
发明人： Kuo-Ji Chen , Wen-Chuan Chiang , Huey-Chi Chu , Ming-Hsiang Song , Chen-Jong Wang
IPC分类号： H01L49/02 , H01L29/92
CPC分类号： H01L28/60 , H01L28/75 , H01L29/92
摘要： Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.
摘要翻译：公开了用于制造金属 - 绝缘体 - 金属（MIM）电容器的方法和装置。 MIM电容器可以包括电极，其可以是具有瓶颈的顶部或底部电极。 MIM电容器可以包括与通孔的侧壁接触的电极，其可以是顶部或底部电极。当泄漏电流超过规格时，电极的侧壁接触或瓶颈可燃烧形成高阻抗路径，而电极的侧壁接触或瓶颈对于正常的MIM操作没有影响。 MIM电容器可用作去耦电容器。

7. 发明授权

US06207491B1 Method for preventing silicon substrate loss in fabricating semiconductor device 有权
标题翻译：在制造半导体器件中防止硅衬底损耗的方法
公开(公告)号：US06207491B1
公开(公告)日：2001-03-27
申请号：US09258087
申请日：1999-02-25
申请人： Huey-Chi Chu , Yeh-Sen Lin , Chia-Ching Tung
发明人： Huey-Chi Chu , Yeh-Sen Lin , Chia-Ching Tung
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L27/10873
摘要： The present invention discloses a method for eliminating leakage current in a semiconductor device by preventing silicon loss in a first area of a substrate during fabricating the semiconductor device. The method according to the preferred embodiment of the present invention includes the following steps. Firstly, form a first gate structure on a second area of the substrate, and form a first structure together with a second structure on the first area of the substrate. Then form a dielectric layer on the topography of the wafer. Next, etch a thickness of the dielectric layer until about 200-1000 angstroms in thickness of the dielectric layer is remained. Subsequently, form a photoresist pattern on the first area of the substrate, and etch the exposed second portion of the dielectric layer to form spacers of the first gate structure. The spacers and the gate structure constitute a gate electrode of a first transistor. Next, form a source region and a drain region in the substrate, wherein the gate electrode, the source region, and the drain region constitute a first transistor, then remove the photoresist pattern. Finally, form a second transistor, a capacitor, and a control line in the first area of the substrate, wherein the first structure and the second structure is formed on the first area of the substrate.
摘要翻译：本发明公开了一种通过在制造半导体器件期间防止衬底的第一区域中的硅损耗来消除半导体器件中的漏电流的方法。根据本发明的优选实施方案的方法包括以下步骤。首先，在基板的第二区域上形成第一栅极结构，并在基板的第一区域上与第二结构一起形成第一结构。然后在晶片的形貌上形成介电层。接下来，蚀刻介电层的厚度，直到保留介电层的厚度约为200-1000埃。随后，在衬底的第一区域上形成光致抗蚀剂图案，并且蚀刻介电层的暴露的第二部分以形成第一栅极结构的间隔物。间隔物和栅极结构构成第一晶体管的栅电极。接下来，在衬底中形成源极区域和漏极区域，其中栅极电极，源极区域和漏极区域构成第一晶体管，然后去除光致抗蚀剂图案。最后，在基板的第一区域中形成第二晶体管，电容器和控制线，其中第一结构和第二结构形成在基板的第一区域上。

8. 发明授权

US08436408B2 Semiconductor device with decoupling capacitor design 有权
标题翻译：具有去耦电容设计的半导体器件
公开(公告)号：US08436408B2
公开(公告)日：2013-05-07
申请号：US12212096
申请日：2008-09-17
申请人： Kuo-Chi Tu , Huey-Chi Chu , Kuo-Cheng Ching
发明人： Kuo-Chi Tu , Huey-Chi Chu , Kuo-Cheng Ching
IPC分类号： H01L27/108
CPC分类号： H01L23/5223 , H01L27/0629 , H01L27/10852 , H01L27/10894 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a circuit module having a plurality of active components coupled between a pair of supply nodes, and a capacitive decoupling module coupled to the circuit module. The capacitive decoupling module includes a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the pair of supply nodes, wherein a voltage between the supply nodes is divided across the plurality of MiM capacitors, thereby reducing voltage stress on the capacitors.
摘要翻译：集成电路包括具有耦合在一对电源节点之间的多个有源元件的电路模块和耦合到电路模块的电容去耦模块。电容去耦模块包括串联耦合在一对电源节点之间的多个金属 - 绝缘体 - 金属（MiM）电容器，其中供电节点之间的电压在多个MiM电容器之间分开，从而减小电容器上的电压应力。

9. 发明申请

US20100065944A1 SEMICONDUCTOR DEVICE WITH DECOUPLING CAPACITOR DESIGN 有权
标题翻译：具有解耦电容器设计的半导体器件
公开(公告)号：US20100065944A1
公开(公告)日：2010-03-18
申请号：US12212096
申请日：2008-09-17
申请人： Kuo-Chi TU , Huey-Chi Chu , Kuo-Cheng Ching
发明人： Kuo-Chi TU , Huey-Chi Chu , Kuo-Cheng Ching
IPC分类号： H01L29/92
CPC分类号： H01L23/5223 , H01L27/0629 , H01L27/10852 , H01L27/10894 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a circuit module having a plurality of active components coupled between a pair of supply nodes, and a capacitive decoupling module coupled to the circuit module. The capacitive decoupling module includes a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the pair of supply nodes, wherein a voltage between the supply nodes is divided across the plurality of MiM capacitors, thereby reducing voltage stress on the capacitors.
摘要翻译：集成电路包括具有耦合在一对电源节点之间的多个有源元件的电路模块和耦合到电路模块的电容去耦模块。电容去耦模块包括串联耦合在一对电源节点之间的多个金属 - 绝缘体 - 金属（MiM）电容器，其中供电节点之间的电压在多个MiM电容器之间分开，从而减小电容器上的电压应力。

10. 发明授权

US07115935B2 Embedded DRAM for metal-insulator-metal (MIM) capacitor structure 有权
标题翻译：金属绝缘体金属（MIM）电容器结构的嵌入式DRAM
公开(公告)号：US07115935B2
公开(公告)日：2006-10-03
申请号：US10822197
申请日：2004-04-09
申请人： Kuo-Chi Tu , Chun-Yao Chen , Huey-Chi Chu
发明人： Kuo-Chi Tu , Chun-Yao Chen , Huey-Chi Chu
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L27/10811 , H01L27/10894 , H01L27/10897 , H01L28/91
摘要： A method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is described. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the substrate and in a memory area of the substrate and providing node contact plugs to node contact regions within the substrate in the memory area. Thereafter, capacitors are fabricated in a twisted trench in a self-aligned copper process.
摘要翻译：描述了在嵌入式DRAM工艺中制造金属 - 绝缘体 - 金属电容器的方法。多个接触插塞通过绝缘层提供到衬底中的半导体器件结构，其中接触插塞形成在衬底的逻辑区域中并且在衬底的存储区域中并且将节点接触插塞提供到衬底内的节点接触区域底物在记忆区。此后，电容器在自对准铜工艺中以扭曲的沟槽制造。

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