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1. 发明授权

US5658821A Method of improving uniformity of metal-to-poly capacitors composed by polysilicon oxide and avoiding device damage 失效
标题翻译：提高由多晶硅氧化物组成的金属对多晶硅电容器的均匀性，避免器件损坏的方法
公开(公告)号：US5658821A
公开(公告)日：1997-08-19
申请号：US721668
申请日：1996-09-27
申请人： Hsin-Pai Chen , Sue-Mei Ku , Pei-Hung Chen , Chih-Shih Wei
发明人： Hsin-Pai Chen , Sue-Mei Ku , Pei-Hung Chen , Chih-Shih Wei
IPC分类号： H01L21/02 , H01L21/321 , H01L21/70
CPC分类号： H01L28/40 , H01L21/32105
摘要： A method of forming capacitors comprising polysilicon, polysilicon oxide, metal is described which significantly improves uniformity of capacitance across the silicon integrated circuit wafer and avoids damage to electrical contact regions. A first layer of polysilicon oxide is formed on a polysilicon first capacitor plate. The wafer is then dipped in a buffered oxide etch or subjected to a dry anisotropic etch. The etching conditions the polysilicon layer so that subsequent polysilicon oxide growth is very uniform and controllable. A second polysilicon oxide layer is then formed on the polysilicon first capacitor plate. A layer of silicon nitride is formed on the polysilicon oxide and a second capacitor plate is formed on the layer of silicon nitride completing the capacitor. Improved capacitance uniformity across the wafer is achieved and device damage is avoided.
摘要翻译：描述了形成包括多晶硅，多晶硅氧化物，金属的电容器的方法，其显着地提高了跨越硅集成电路晶片的电容的均匀性并且避免了对电接触区域的损坏。在多晶硅第一电容器板上形成第一层多晶硅氧化物。然后将晶片浸入缓冲氧化物蚀刻中或进行干法各向异性蚀刻。蚀刻条件使多晶硅层成为后续的多晶硅氧化物生长非常均匀和可控的。然后在多晶硅第一电容器板上形成第二多晶硅氧化物层。在多晶硅氧化物上形成氮化硅层，在形成电容器的氮化硅层上形成第二电容器板。实现了跨晶片的改善的电容均匀性，避免了器件损坏。

2. 发明授权

US4966868A Process for selective contact hole filling including a silicide plug 失效
标题翻译：包括硅化物塞的选择性接触孔填充的方法
公开(公告)号：US4966868A
公开(公告)日：1990-10-30
申请号：US406881
申请日：1989-09-13
申请人： Venkatesan Murali , Chih-Shih Wei , David B. Fraser
发明人： Venkatesan Murali , Chih-Shih Wei , David B. Fraser
IPC分类号： H01L21/285 , H01L21/768
CPC分类号： H01L21/76879 , H01L21/28525
摘要： A process which provides for self-aligned contact hole filling leading to complete planarization and low contact resistance at the same time, without the use of additional lithographic masking procedures is described. Further, the resultant conductive plug eliminates spiking problems between aluminum and silicon during a subsequent alloying process. In an embodiment, a selective polysilicon layer is deposited and appropriately doped; a second undoped selective silicon layer is then deposited, followed by a refractory metal layer, These layers are heated to produce a self-aligned refractory metal silicide plug.
摘要翻译：描述了一种提供自对准接触孔填充的过程，导致完全平坦化和同时具有低接触电阻，而不使用额外的光刻掩模程序。此外，所得到的导电插塞在随后的合金化过程中消除了铝和硅之间的尖峰问题。在一个实施例中，选择性多晶硅层被沉积并适当掺杂; 然后沉积第二未掺杂的选择性硅层，然后沉积难熔金属层。将这些层加热以产生自对准难熔金属硅化物塞。

3. 发明申请

US20100088129A1 Technology Selection and Pricing System 审中-公开
标题翻译：技术选择与定价系统
公开(公告)号：US20100088129A1
公开(公告)日：2010-04-08
申请号：US12245247
申请日：2008-10-03
申请人： Chih-Shih Wei , Ji-Chung Huang , Ssu-Ying Chen , Hwa-Yu Yang
发明人： Chih-Shih Wei , Ji-Chung Huang , Ssu-Ying Chen , Hwa-Yu Yang
IPC分类号： G06Q10/00 , G06Q30/00 , G06Q50/00
CPC分类号： G06Q30/02 , G06Q10/04 , G06Q30/0283 , G06Q50/04 , Y02P90/30
摘要： A method of selecting a technology for manufacturing an integrated circuit includes designating candidate technologies for manufacturing the integrated circuit; generating design and performance data from the integrated circuit, wherein the design and performance data are generated for each of the candidate technologies; and generating die prices from the integrated circuit, wherein the die prices are generated for each of the candidate technologies.
摘要翻译：选择用于制造集成电路的技术的方法包括指定用于制造集成电路的候选技术; 从集成电路产生设计和性能数据，其中为每个候选技术生成设计和性能数据; 并从集成电路产生模具价格，其中针对每个候选技术产生模具价格。

4. 发明授权

US5843831A Process independent alignment system 失效
标题翻译：过程独立对齐系统
公开(公告)号：US5843831A
公开(公告)日：1998-12-01
申请号：US782702
申请日：1997-01-13
申请人： Wen-Jye Chung , Bor-Ping Jang , Chih-Shih Wei
发明人： Wen-Jye Chung , Bor-Ping Jang , Chih-Shih Wei
IPC分类号： G03F9/00 , H01L21/68 , H01L23/544 , H01L21/76
CPC分类号： G03F9/7084 , G03F9/7076 , H01L21/681 , H01L23/544 , H01L2223/54453 , H01L2924/0002
摘要： A method is disclosed for aligning wafers independent of the processes to which a wafer is subjected. In prior art, it is found that when aligning wafers from the front or device side, the alignment of the masks vary because of the variations on the topography of the particular layer in process. Since the topography of a layer is influenced by the planarization processes used and by the cumulative effect of the number of underlying features that are disposed on top of each other, severe misalignments can occur causing defective parts. The problem is eliminated by forming alignment marks on the backside of the wafer, and performing alignment with respect to the backside marks by projecting IR energy through an IR transparent stage placed under the backside of the wafer and using an IR microscope. An alignment system capable of performing process independent alignment is also disclosed.
摘要翻译：公开了一种用于对准晶片的方法，而不管晶片受到的处理。在现有技术中，发现当从正面或器件侧对准晶片时，掩模的对准由于处理中的特定层的形貌的变化而变化。由于层的形貌受到所使用的平面化处理和被布置在彼此顶部的底层特征的数量的累积效应的影响，因此可能导致严重的不对准而导致缺陷部件。通过在晶片的背面形成对准标记来消除该问题，并通过将IR能量投射到放置在晶片背面的IR透明级并使用IR显微镜来进行相对于背面标记的对准。还公开了一种能够执行过程独立对准的对准系统。

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