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1. 发明授权

US06563735B1 NOR-structured semiconductor memory device 有权
标题翻译： NOR结构的半导体存储器件
公开(公告)号：US06563735B1
公开(公告)日：2003-05-13
申请号：US10117148
申请日：2002-04-04
申请人： Hsin-Chien Chen , Gin-Liang Chen , Hsin-Yi Ho , Chun-Hsiung Hung , Ho-Chun Liou
发明人： Hsin-Chien Chen , Gin-Liang Chen , Hsin-Yi Ho , Chun-Hsiung Hung , Ho-Chun Liou
IPC分类号： G11C1604
CPC分类号： G11C16/0491
摘要： A NOR-structured semiconductor memory device with a novel configuration of bit line connection is disclosed. The NOR-structured semiconductor memory device comprises a semiconductor memory cell array electrically connected to a plurality of bit lines. The plurality of bit lines are divided into at least four bit line groups. At least two bit lines of each bit line group are coupled to a main bit line through at least two bit line transistors, respectively. Furthermore, the bit lines of the NOR-structured semiconductor memory device are arranged in such a way that at least four adjacent bit lines thereof are selected from four different bit line groups and coupled to four different main bit lines, respectively. During a programming or data reading operation, two adjacent bit lines of the four adjacent bit lines are supplied with a programming voltage or sense current while the other two adjacent bit lines are grounded. Therefore, the NOR-structured semiconductor memory device successfully prevents the programming disturbance or correctly determines the data stored in memory cells at a high speed because no leakage current path is formed.
摘要翻译：公开了具有位线连接的新颖结构的NOR结构的半导体存储器件。 NOR结构的半导体存储器件包括电连接到多个位线的半导体存储单元阵列。多个位线被分成至少四个位线组。每个位线组的至少两个位线分别通过至少两个位线晶体管耦合到主位线。此外，NOR结构半导体存储器件的位线被布置成使得其中至少四个相邻的位线分别从四个不同的位线组中选择并且分别耦合到四个不同的主位线。在编程或数据读取操作期间，四个相邻位线中的两个相邻位线被提供有编程电压或感测电流，而另外两个相邻位线接地。因此，由于没有形成泄漏电流路径，所以NOR结构的半导体存储器件成功地防止了编程干扰或者以高速正确地确定存储在存储单元中的数据。

2. 发明授权

US06845052B1 Dual reference cell sensing scheme for non-volatile memory 有权
标题翻译：用于非易失性存储器的双参考单元感测方案
公开(公告)号：US06845052B1
公开(公告)日：2005-01-18
申请号：US10250040
申请日：2003-05-30
申请人： Hsin-Yi Ho , Nai-Ping Kuo , Chun-Hsiung Hung , Gin-Liang Chen , Wen-Chiao Ho , Ho-Chun Liou
发明人： Hsin-Yi Ho , Nai-Ping Kuo , Chun-Hsiung Hung , Gin-Liang Chen , Wen-Chiao Ho , Ho-Chun Liou
IPC分类号： G11C7/06 , G11C7/14 , G11C16/28 , G11C7/02
CPC分类号： G11C7/14 , G11C7/062 , G11C16/28 , G11C2207/2227
摘要： The present invention provides a dual reference cell sensing scheme for non-volatile memory. A high voltage reference cell and a low voltage reference cell are individually coupled to two sense amplifiers for providing two distinct reference voltages for comparison against the memory cell voltage. The output of the two sense amplifiers is further connected to a second stage sense amplifier to determine the status of the memory. The dual reference cell sensing scheme provides an increased sensing window which increases performance under low voltage application. The dual reference cell sensing scheme can be implemented by either voltage-based, current-based, or ground.
摘要翻译：本发明提供了一种用于非易失性存储器的双参考单元感测方案。高电压参考单元和低电压参考单元分别耦合到两个读出放大器，用于提供用于与存储单元电压进行比较的两个不同的参考电压。两个读出放大器的输出进一步连接到第二级读出放大器以确定存储器的状态。双参考电池感测方案提供增加的感测窗口，其在低电压应用下增加性能。双参考电池感测方案可以通过基于电压，基于电流或接地来实现。

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