专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130139593A1 INERTIAL SENSOR WITH STRESS ISOLATION STRUCTURE 审中-公开
标题翻译：具有应力隔离结构的惯性传感器
公开(公告)号：US20130139593A1
公开(公告)日：2013-06-06
申请号：US13480884
申请日：2012-05-25
申请人： Hsieh-Shen Hsieh , Wei-leun Fang
发明人： Hsieh-Shen Hsieh , Wei-leun Fang
IPC分类号： G01P15/00
CPC分类号： G01P15/09 , G01P15/123 , G01P15/125 , G01P15/18 , G01P2015/0814 , G01P2015/0842
摘要： An inertial sensor with stress isolation structure includes a substrate, a suspension bridge, a guard ring and an electromechanical conversion mechanism. The substrate has a housing trough and an annular wall surrounding the housing trough. The suspension bridge is located in the housing trough and connected to the annular wall. The guard ring is connected to the suspension bridge and suspended in the housing trough. The suspension bridge is located between the substrate and guard ring. The electromechanical conversion mechanism is connected to and surrounded by the guard ring. Through the guard ring, interferences of applied forces to the electromechanical conversion mechanism can be reduced, precision of the inertial sensor can be improved, and performance impact caused by succeeding element package process can also be reduced. Thus package, test and calibration processes can be simplified to lower production cost.
摘要翻译：具有应力隔离结构的惯性传感器包括基板，吊桥，保护环和机电转换机构。衬底具有壳体槽和围绕壳体槽的环形壁。吊桥位于外壳槽中并与环形壁连接。防护环连接到吊桥并悬挂在外壳槽中。吊桥位于基板和防护环之间。机电转换机构连接保护环并被保护环围绕。通过防护环，可以降低对机电转换机构的施加力的干扰，可以提高惯性传感器的精度，并且还可以降低由元件封装过程引起的性能影响。因此，可以简化封装，测试和校准过程，以降低生产成本。

2. 发明申请

US20120099063A1 ALIGNMENT FILM FOR SPONTANEOUSLY ALIGNING LIQUID CRYSTAL 审中-公开
标题翻译：用于自发调整液晶的对准膜
公开(公告)号：US20120099063A1
公开(公告)日：2012-04-26
申请号：US13091563
申请日：2011-04-21
申请人： Chi-Tsung Hung , Tsung-Ta Tang , Chi-Yuan Hung , Ru-Pin Chao , Wei-leun Fang
发明人： Chi-Tsung Hung , Tsung-Ta Tang , Chi-Yuan Hung , Ru-Pin Chao , Wei-leun Fang
IPC分类号： G02F1/1337
CPC分类号： G02F1/133707
摘要： An alignment film for spontaneously aligning liquid crystal is used to align a plurality of liquid crystal grains and comprises a first substrate, a second substrate, a liquid crystal layer, a first transparent conductive layer, a second transparent conductive layer, a first alignment film and a second alignment film. The first and second alignment films are made of anodic aluminum oxide and have a plurality of nanometric pores respectively. The liquid crystal layer is interposed between the first and second alignment films. The nanometric pores of the first and second alignment films induce the liquid crystal grains to align spontaneously. Thereby, the problems of contamination, denatured material and non-uniform alignment, which are caused by the conventional liquid crystal alignment technology, can be solved. Further, the fabrication process of the alignment film can integrate with the current LCD process to fabricate a large-size LCD panel.
摘要翻译：使用用于自发对准液晶的取向膜来对准多个液晶晶粒，并且包括第一基板，第二基板，液晶层，第一透明导电层，第二透明导电层，第一取向膜和第二取向膜。第一和第二取向膜由阳极氧化铝制成，分别具有多个纳米孔。液晶层介于第一和第二取向膜之间。第一和第二取向膜的纳米孔引起液晶粒子自发对准。因此，可以解决由常规液晶取向技术引起的污染，变性材料和不均匀取向的问题。此外，取向膜的制造工艺可以与当前的LCD工艺集成以制造大尺寸的LCD面板。

3. 发明授权

US08679974B2 Method for fabricating interconnecting lines inside via holes of semiconductor device 有权
标题翻译：在半导体器件的通孔内部形成互连线的方法
公开(公告)号：US08679974B2
公开(公告)日：2014-03-25
申请号：US13416627
申请日：2012-03-09
申请人： Wei-leun Fang , Chia Han Lin , Feng Yu Lee
发明人： Wei-leun Fang , Chia Han Lin , Feng Yu Lee
IPC分类号： H01L21/44
CPC分类号： H01L21/76898
摘要： A method for fabricating interconnecting lines inside via holes of a semiconductor device comprises steps of providing a template having a receiving trench and a connection surface both on the same side of the template; filling an electric-conduction material into the receiving trench; connecting a substrate having at least one via hole with the connection surface to interconnect the via hole with the receiving trench; heating the electric-conduction material to a working temperature to liquefy a portion of the electric-conduction material and make it flows from the receiving trench into the via hole; and cooling the electric-conduction material to form an interconnecting line inside the via hole. The present invention fabricates interconnecting lines by a heat-forming method, which features simple steps and has advantages of shorter fabrication time, lower fabrication complexity, higher fabrication efficiency, higher yield and lower fabrication cost.
摘要翻译：一种用于在半导体器件的通孔内部制造互连线的方法包括以下步骤：在模板的同一侧提供具有接收沟槽和连接表面的模板; 将导电材料填充到所述接收沟槽中; 将具有至少一个通孔的基板与所述连接表面连接，以将所述通孔与所述接收沟槽相互连接; 将导电材料加热到工作温度以液化导电材料的一部分并使其从接收槽流入通孔; 并且冷却所述导电材料以在所述通孔内部形成互连线。本发明通过热成型方法制造互连线，其特征在于简单的步骤，并且具有制造时间缩短，制造复杂性更低，制造效率更高，成品率更高，制造成本更低的优点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式