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1. 发明授权

US09103884B2 De-embedding on-wafer devices 有权
标题翻译：去嵌入晶圆器件
公开(公告)号：US09103884B2
公开(公告)日：2015-08-11
申请号：US12963511
申请日：2010-12-08
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Sa-Lly Liu
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Sa-Lly Liu
IPC分类号： G01R31/26 , G01R31/3185 , G11C29/56 , H01L21/66
CPC分类号： G01R31/2601 , G01R1/0491 , G01R31/2644 , G01R31/318511 , G11C29/56 , G11C2029/5602 , H01L22/34
摘要： A transmission line is provided. In one embodiment, the transmission line comprises a substrate, a well within the substrate, a shielding layer over the well, and a plurality of intermediate metal layers over the shielding layer, the plurality of intermediate metal layers coupled by a plurality of vias. The transmission line further includes a top metal layer over the plurality of intermediate metal layers. A test structure for de-embedding an on-wafer device, and a wafer are also disclosed.
摘要翻译：提供传输线。在一个实施例中，传输线包括衬底，衬底内的阱，阱上的屏蔽层以及屏蔽层上的多个中间金属层，多个中间金属层通过多个通孔耦合。传输线还包括多个中间金属层上的顶部金属层。还公开了用于去嵌入晶片装置和晶片的测试结构。

2. 发明授权

US09087840B2 Slot-shielded coplanar strip-line compatible with CMOS processes 有权
标题翻译：与CMOS工艺兼容的插槽屏蔽共面带状线
公开(公告)号：US09087840B2
公开(公告)日：2015-07-21
申请号：US12917285
申请日：2010-11-01
申请人： Yu-Ling Lin , Hsiao-Tsung Yen , Ho-Hsiang Chen , Chin-Wei Kuo , Chewn-Pu Jou
发明人： Yu-Ling Lin , Hsiao-Tsung Yen , Ho-Hsiang Chen , Chin-Wei Kuo , Chewn-Pu Jou
IPC分类号： H01L23/14 , H01L23/522 , H01L23/66 , H01L27/06
CPC分类号： H01L23/5225 , H01L23/5226 , H01L23/528 , H01L23/64 , H01L23/66 , H01L27/0629 , H01L2223/6627 , H01L2924/0002 , H01L2924/00
摘要： A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.
摘要翻译：带状线包括在衬底上延伸穿过多个电介质层的接地平面; 在基板上并在接地平面的一侧的信号线; 在信号线下方和第一金属层中的第一多个金属条，其中所述第一多个金属条彼此平行并且彼此间隔开; 以及信号线下方的第二多个金属条，并且在第一金属层上方的第二金属层中。第二多个金属带垂直地与空间重叠。第一多个金属条通过接地平面电耦合到第二多个金属条，并且不通过物理地接触第一多个金属条和第二多个金属条。

3. 发明申请

US20130099352A1 STRUCTURE AND METHOD FOR A HIGH-K TRANSFORMER WITH CAPACITIVE COUPLING 有权
标题翻译：具有电容耦合的高K变压器的结构和方法
公开(公告)号：US20130099352A1
公开(公告)日：2013-04-25
申请号：US13280786
申请日：2011-10-25
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5222 , H01F17/0013 , H01L21/76805 , H01L21/76877 , H01L23/5225 , H01L23/5227 , H01L23/528 , H01L23/552 , H01L23/642 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.
摘要翻译：本发明提供一种半导体器件。半导体器件包括具有集成电路（IC）器件的半导体衬底; 布置在半导体衬底上并与IC器件耦合的互连结构; 以及设置在半导体衬底上并集成在互连结构中的变压器。变压器包括第一导电特征; 与所述第一导电特征电感耦合的第二导电特征; 电连接到第一导电特征的第三导电特征; 以及电连接到第二导电特征的第四导电特征。第三和第四导电特征被设计和配置为电容耦合以增加变压器的耦合系数。

4. 发明申请

US20120146741A1 TRANSFORMER WITH BYPASS CAPACITOR 有权
标题翻译：带旁路电容器的变压器
公开(公告)号：US20120146741A1
公开(公告)日：2012-06-14
申请号：US12963701
申请日：2010-12-09
申请人： Hsiao-Tsung YEN , Yu-Ling Lin , Ying-Ta Lu , Chin-Wei Kuo , Ho-Hsiang Chen
发明人： Hsiao-Tsung YEN , Yu-Ling Lin , Ying-Ta Lu , Chin-Wei Kuo , Ho-Hsiang Chen
IPC分类号： H03H7/42 , H01L21/00
CPC分类号： H01L23/5227 , H01F17/0006 , H01F2017/0086 , H01L23/5223 , H01L2924/0002 , Y10T29/41 , H01L2924/00
摘要： An electronic device comprises first, second and third inductors connected in series and formed in a metal layer over a semiconductor substrate. The first and second inductors have a mutual inductance with each other. The second and third inductors having a mutual inductance with each other. A first capacitor has a first electrode connected to a first node. The first node is conductively coupled between the first and second inductors. A second capacitor has a second electrode connected to a second node. The second node is conductively coupled between the second and third inductors.
摘要翻译：电子器件包括串联连接并形成在半导体衬底上的金属层中的第一，第二和第三电感器。第一和第二电感器具有彼此的互感。第二和第三电感器具有彼此的互感。第一电容器具有连接到第一节点的第一电极。第一节点电导耦合在第一和第二电感器之间。第二电容器具有连接到第二节点的第二电极。第二节点电导耦合在第二和第三电感器之间。

5. 发明申请

US20130228894A1 STRUCTURE AND METHOD FOR A FISHBONE DIFFERENTIAL CAPACITOR 有权
标题翻译： FISHBONE差分电容器的结构和方法
公开(公告)号：US20130228894A1
公开(公告)日：2013-09-05
申请号：US13411052
申请日：2012-03-02
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号： H01L27/06 , H01L21/768
CPC分类号： H01L23/5223 , H01L28/60 , H01L28/88 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor structure disposed on the substrate. The capacitor structure includes a first conductive component; a second conductive component and a third conductive component symmetrically configured on opposite sides of the first conductive component. The first, second and third conductive components are separated from each other by respective dielectric material.
摘要翻译：本发明提供集成电路。集成电路包括具有由第一轴线和垂直于第一轴线的第二轴线限定的表面的基板; 以及设置在基板上的电容器结构。电容器结构包括第一导电元件; 对称地配置在第一导电部件的相对侧上的第二导电部件和第三导电部件。第一，第二和第三导电部件通过相应的介电材料彼此分离。

6. 发明授权

US09087838B2 Structure and method for a high-K transformer with capacitive coupling 有权
标题翻译：具有电容耦合的高K变压器的结构和方法
公开(公告)号：US09087838B2
公开(公告)日：2015-07-21
申请号：US13280786
申请日：2011-10-25
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号： H01L23/52 , H01L21/02 , H01L23/522 , H01L23/64 , H01L49/02
CPC分类号： H01L23/5222 , H01F17/0013 , H01L21/76805 , H01L21/76877 , H01L23/5225 , H01L23/5227 , H01L23/528 , H01L23/552 , H01L23/642 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.
摘要翻译：本发明提供一种半导体器件。半导体器件包括具有集成电路（IC）器件的半导体衬底; 布置在半导体衬底上并与IC器件耦合的互连结构; 以及设置在半导体衬底上并集成在互连结构中的变压器。变压器包括第一导电特征; 与所述第一导电特征电感耦合的第二导电特征; 电连接到第一导电特征的第三导电特征; 以及电连接到第二导电特征的第四导电特征。第三和第四导电特征被设计和配置为电容耦合以增加变压器的耦合系数。

7. 发明授权

US08674883B2 Antenna using through-silicon via 有权
标题翻译：天线使用硅通孔
公开(公告)号：US08674883B2
公开(公告)日：2014-03-18
申请号：US13114828
申请日：2011-05-24
申请人： Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Lin , Chin-Wei Kuo , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Lin , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号： H01Q1/38
CPC分类号： H01Q1/50 , G06F17/5068 , H01L23/48 , H01L23/481 , H01L23/66 , H01L25/0657 , H01L25/074 , H01L2223/6616 , H01L2223/6677 , H01L2225/06531 , H01L2225/06541 , H01L2225/06548 , H01L2924/0002 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/10333 , H01L2924/10335 , H01L2924/1421 , H01L2924/1461 , H01Q1/2283 , H01Q1/38 , H01Q5/357 , H01Q9/0421 , H01Q9/0442 , H01Q9/145 , Y10T29/49016 , H01L2924/00
摘要： An antenna includes a substrate and a top plate disposed over the substrate. At least one feed line is connected to the top plate, and each feed line comprises a first through-silicon via (TSV) structure passing through the substrate. At least one ground line is connected to the top plate, and each ground line comprises a second TSV structure passing through the substrate. The top plate is electrically conductive, and the at least one feed line is arranged to carry a radio frequency signal. The at least one ground line is arranged to be coupled to a ground.
摘要翻译：天线包括衬底和设置在衬底上的顶板。至少一个进料管线连接到顶板，并且每个进料管线包括穿过基材的第一穿硅通孔（TSV）结构。至少一个接地线连接到顶板，并且每个接地线包括穿过衬底的第二TSV结构。顶板是导电的，并且至少一个馈线布置成承载射频信号。所述至少一个接地线被布置成联接到地面。

8. 发明申请

US20130277794A1 Tuning the Efficiency in the Transmission of Radio-Frequency Signals Using Micro-Bumps 有权
标题翻译：调整使用微型轰击发射射频信号的效率
公开(公告)号：US20130277794A1
公开(公告)日：2013-10-24
申请号：US13841577
申请日：2013-03-15
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Cheng-Hung Lee , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Cheng-Hung Lee , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号： H01L23/60
CPC分类号： H01L23/60 , H01L23/66 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L27/0248 , H01L2223/6677 , H01L2224/0401 , H01L2224/05023 , H01L2224/05073 , H01L2224/05147 , H01L2224/05567 , H01L2224/05568 , H01L2224/05655 , H01L2224/13083 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/16145 , H01L2224/16148 , H01L2224/16225 , H01L2224/16238 , H01L2224/17517 , H01L2224/81455 , H01L2225/06513 , H01L2924/00014 , H01L2924/01029 , H01L2924/13091 , H01L2924/14 , H01L2924/1421 , H01L2924/15192 , H01L2924/15311 , H01L2924/19104 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2224/131 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump.
摘要翻译：一种器件包括：裸片，包括主电路和耦合到主电路的第一焊盘。包括第二垫的工件被结合到模具。第一多个微凸块在第一和第二焊盘之间串联电耦合。多个微型凸块中的每一个包括连接模具的第一端和连接工件的第二端。微凸块与模具和工件结合。第二焊盘电耦合到微凸起。

9. 发明申请

US20130246990A1 SYSTEM AND METHOD FOR MODELING THROUGH SILICON VIA 有权
标题翻译：通过硅建模的系统和方法
公开(公告)号：US20130246990A1
公开(公告)日：2013-09-19
申请号：US13419959
申请日：2012-03-14
申请人： Hsiao-Tsung YEN , Yu-Ling Lin , Chin-Wei Kuo
发明人： Hsiao-Tsung YEN , Yu-Ling Lin , Chin-Wei Kuo
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H01L23/49827 , H01L2224/13 , H01L2224/16225 , H01L2924/15311
摘要： A computer implemented system comprises a processor programmed to analyze a circuit to determine a response of the circuit to an input radio frequency (RF) signal, for at least one of designing, manufacturing, and testing the circuit. An interposer model is tangibly embodied in a non-transitory machine readable storage medium to be accessed by the processor. The interposer model is processed by the computer to output data representing a response of a though substrate via (TSV) to the radio frequency (RF) signal. The interposer model comprises a plurality of TSV models. Each TSV model has a respective three-port network. One of the ports of each three-port network is a floating node. The floating nodes of each of the three-port networks are connected to each other.
摘要翻译：计算机实现的系统包括被编程为分析电路以确定电路对输入射频（RF）信号的响应的处理器，用于设计，制造和测试电路中的至少一个。中介层模型有形地体现在待处理器访问的非暂时机器可读存储介质中。内插器模型由计算机处理以将表示通过（TSV）的基板的响应的数据输出到射频（RF）信号。内插器模型包括多个TSV模型。每个TSV模型都有相应的三端口网络。每个三端口网络的一个端口是浮动节点。每个三端口网络的浮动节点彼此连接。

10. 发明申请

US20130032799A1 Apparatus and Methods for De-Embedding Through Substrate Vias 有权
标题翻译：通过基板通孔去嵌入的装置和方法
公开(公告)号：US20130032799A1
公开(公告)日：2013-02-07
申请号：US13197602
申请日：2011-08-03
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Victor Chih Yuan Chang , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Victor Chih Yuan Chang , Min-Chie Jeng
IPC分类号： H01L23/528 , H01L21/66
CPC分类号： G01R31/2644 , H01L22/34 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method includes providing on a substrate having at least two through substrate vias (“TSVs”) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs; measuring the intrinsic characteristics [L] for a first and a second test structure on the substrate including two pads coupled with a transmission line of length L; using simultaneous solutions of ABCD matrix or T matrix form equations, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines; de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs.
摘要翻译：一种方法包括在具有至少两个通过衬底通孔（TSV）的衬底上提供多个测试结构，用于对包括至少两个TSV的被测器件（DUT）的固有特性的测量进行解嵌入; 测量包括与长度为L的传输线耦合的两个焊盘的衬底上的第一和第二测试结构的固有特性[L] 使用ABCD矩阵或T矩阵形式方程的同时解，以及测量的固有特性，求解焊盘和传输线的固有特性; 使用焊盘和传输线的固有特性来解嵌第三和第四测试结构的测量; 并且对于BM_L和BM_LX使用ABCD矩阵或T矩阵形式方程的同时解，以及测量的固有特性，求解TSV的固有特性。

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