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1. 发明授权

US08441957B2 Apparatus and method of remote PHY auto-negotiation 有权
标题翻译：远程PHY自动协商的设备和方法
公开(公告)号：US08441957B2
公开(公告)日：2013-05-14
申请号：US11272148
申请日：2005-11-14
申请人： Howard A. Baumer , Scott McDaniel , Gary S. Huff , John Louie
发明人： Howard A. Baumer , Scott McDaniel , Gary S. Huff , John Louie
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26 , G06F15/173
CPC分类号： H04L41/00 , H04L12/40136 , H04L41/12
摘要： A communications network includes a management device and a remote device. The remote device includes a physical layer device (PHY) coupled to a link partner. An independent station manager of the remote device provides the bi-directional exchange of management information between the PHY and a serial-to-parallel (S/P) interface connecting the remote device and the management device. A station manager of the management device provides the bi-directional exchange of management information between the S/P interface and a Media Access Controller (MAC) of the management device. The independent station manager and the station manager transmit initiation messages, formatted according to a message template of an Auto-Negotiation (AN) routine of the S/P interface reserved for customization, to reserve an embedded management channel for the transfer of management information. Management information messages, formatted according to a message template of the AN routine, are subsequently exchanged, thereby providing Auto-Negotiation of the PHY.
摘要翻译：通信网络包括管理设备和远程设备。远程设备包括耦合到链路伙伴的物理层设备（PHY）。远程设备的独立站管理器在PHY和连接远程设备和管理设备的串行到并行（S / P）接口之间提供管理信息的双向交换。管理装置的站管理器在S / P接口和管理设备的媒体访问控制器（MAC）之间提供管理信息的双向交换。独立站管理者和站管理员根据保留用于定制的S / P接口的自动协商（AN）例程的消息模板传送启动消息，以保留用于传送管理信息的嵌入式管理信道。随后交换根据AN例程的消息模板格式化的管理信息消息，从而提供PHY的自动协商。

2. 发明授权

US08111738B2 Method and transceiver system having a transmit clock signal phase that is phase-locked with a receive clock signal phase 有权
标题翻译：方法和收发机系统具有与接收时钟信号相锁相的发射时钟信号相位
公开(公告)号：US08111738B2
公开(公告)日：2012-02-07
申请号：US12881108
申请日：2010-09-13
申请人： Abbas Amirichimeh , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
发明人： Abbas Amirichimeh , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
IPC分类号： H04B1/38 , H04L7/00 , H04L23/00
CPC分类号： H03K5/135 , H04L7/0012 , H04L7/0091
摘要： A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.
摘要翻译：公开了一种收发器系统，其包括多个收发器芯片。每个收发器芯片包括一个或多个SERDES内核。每个SERDES核心包括一个或多个SERDES通道。每个SERDES通道包括接收通道和发送通道。每个SERDES通道的发送通道与相应的接收通道锁相。收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是一个不同的董事会。每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

3. 发明授权

US07593457B2 Transceiver system and method having a transmit clock signal phase that is phase-locked with a receive clock signal phase 有权
标题翻译：收发器系统和方法具有与接收时钟信号相位锁相的发射时钟信号相位
公开(公告)号：US07593457B2
公开(公告)日：2009-09-22
申请号：US10813363
申请日：2004-03-31
申请人： Abbas Amirichimeh , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
发明人： Abbas Amirichimeh , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
IPC分类号： H04B1/38 , H04L7/00
CPC分类号： H03K5/135 , H04L7/0012 , H04L7/0091
摘要： A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.
摘要翻译：公开了一种收发器系统，其包括多个收发器芯片。每个收发器芯片包括一个或多个SERDES内核。每个SERDES核心包括一个或多个SERDES通道。每个SERDES通道包括接收通道和发送通道。每个SERDES通道的发送通道与相应的接收通道锁相。收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是一个不同的董事会。每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

4. 发明申请

US20110007785A1 Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase 有权
标题翻译：具有与接收时钟信号相锁相的发送时钟信号相位的方法和收发器系统
公开(公告)号：US20110007785A1
公开(公告)日：2011-01-13
申请号：US12881108
申请日：2010-09-13
申请人： Abbas Amirichimeh , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
发明人： Abbas Amirichimeh , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
IPC分类号： H04B1/38
CPC分类号： H03K5/135 , H04L7/0012 , H04L7/0091
摘要： A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.
摘要翻译：公开了一种收发器系统，其包括多个收发器芯片。每个收发器芯片包括一个或多个SERDES内核。每个SERDES核心包括一个或多个SERDES通道。每个SERDES通道包括接收通道和发送通道。每个SERDES通道的发送通道与相应的接收通道锁相。收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是一个不同的董事会。每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

5. 发明授权

US07796682B2 Method and transceiver system having a transmit clock signal phase that is phase-locked with a receive clock signal phase 有权
标题翻译：方法和收发机系统具有与接收时钟信号相锁相的发射时钟信号相位
公开(公告)号：US07796682B2
公开(公告)日：2010-09-14
申请号：US12476207
申请日：2009-06-01
申请人： Abbas Amirichimeh , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
发明人： Abbas Amirichimeh , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
IPC分类号： H04L25/20 , H04L7/00 , H04B1/38
CPC分类号： H03K5/135 , H04L7/0012 , H04L7/0091
摘要： A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.
摘要翻译：公开了一种收发器系统，其包括多个收发器芯片。每个收发器芯片包括一个或多个SERDES内核。每个SERDES核心包括一个或多个SERDES通道。每个SERDES通道包括接收通道和发送通道。每个SERDES通道的发送通道与相应的接收通道锁相。收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是一个不同的董事会。每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

6. 发明申请

US20120201280A1 Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase 有权
标题翻译：具有与接收时钟信号相锁相的发送时钟信号相位的方法和收发器系统
公开(公告)号：US20120201280A1
公开(公告)日：2012-08-09
申请号：US13367282
申请日：2012-02-06
申请人： Abbas AMIRICHIMEH , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
发明人： Abbas AMIRICHIMEH , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
IPC分类号： H04B1/38
CPC分类号： H03K5/135 , H04L7/0012 , H04L7/0091
摘要： A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.
摘要翻译：公开了一种收发器系统，其包括多个收发器芯片。每个收发器芯片包括一个或多个SERDES内核。每个SERDES核心包括一个或多个SERDES通道。每个SERDES通道包括接收通道和发送通道。每个SERDES通道的发送通道与相应的接收通道锁相。收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是一个不同的董事会。每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

7. 发明申请

US20090232192A1 Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase 有权
标题翻译：具有与接收时钟信号相锁相的发送时钟信号相位的方法和收发器系统
公开(公告)号：US20090232192A1
公开(公告)日：2009-09-17
申请号：US12476207
申请日：2009-06-01
申请人： Abbas AMIRICHIMEH , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
发明人： Abbas AMIRICHIMEH , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
IPC分类号： H04B1/38
CPC分类号： H03K5/135 , H04L7/0012 , H04L7/0091
摘要： A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.
摘要翻译：公开了一种收发器系统，其包括多个收发器芯片。每个收发器芯片包括一个或多个SERDES内核。每个SERDES核心包括一个或多个SERDES通道。每个SERDES通道包括接收通道和发送通道。每个SERDES通道的发送通道与相应的接收通道锁相。收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是一个不同的董事会。每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

8. 发明授权

US07545899B2 System and method of phase-locking a transmit clock signal phase with a receive clock signal phase 有权
标题翻译：用接收时钟信号相锁相发射时钟信号相位的系统和方法
公开(公告)号：US07545899B2
公开(公告)日：2009-06-09
申请号：US10813235
申请日：2004-03-31
申请人： Abbas Amirichimeh , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
发明人： Abbas Amirichimeh , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
IPC分类号： H04L7/00 , H04L25/40
CPC分类号： H04L7/0012 , H03M9/00 , H04L7/0079 , H04L7/0091
摘要： Systems and methods for synchronizing a receive clock signal phase with a transmit clock signal phase are presented. A system includes a receiving channel and a transmitting channel, wherein the transmitting channel synchronizes a transmit clock signal phase with a receive clock signal phase based on receive clock signal phase data. A method includes storing a previous receive clock signal phase of a receiving channel and identifying a current receive clock signal phase of the receiving channel. The method further includes determining a phase difference between the previous receive clock signal phase and the current receive clock signal phase, and identifying a direction of the phase difference. The method further includes adjusting a previous transmit clock signal phase of the transmitting channel to a current transmit clock signal phase of the transmitting channel based on the phase difference and direction.
摘要翻译：提出了用于使接收时钟信号相位与发送时钟信号相位同步的系统和方法。系统包括接收信道和发送信道，其中发送信道基于接收时钟信号相位数据将发送时钟信号相位与接收时钟信号相位同步。一种方法包括存储接收信道的先前接收时钟信号相位并识别接收信道的当前接收时钟信号相位。该方法还包括确定先前接收时钟信号相位与当前接收时钟信号相位之间的相位差，以及确定相位差的方向。该方法还包括基于相位差和方向将发送信道的先前发送时钟信号相位调整到发送信道的当前发送时钟信号相位。

9. 发明申请

US20050169417A1 System and method of phase-locking a transmit clock signal phase with a receive clock signal phase 有权
标题翻译：用接收时钟信号相锁相发射时钟信号相位的系统和方法
公开(公告)号：US20050169417A1
公开(公告)日：2005-08-04
申请号：US10813235
申请日：2004-03-31
申请人： Abbas Amirichimeh , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
发明人： Abbas Amirichimeh , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
IPC分类号： H03M9/00 , H04L7/00 , H04L25/00
CPC分类号： H04L7/0012 , H03M9/00 , H04L7/0079 , H04L7/0091
摘要： Systems and methods for synchronizing a receive clock signal phase with a transmit clock signal phase are presented. A system includes a receiving channel and a transmitting channel, wherein the transmitting channel synchronizes a transmit clock signal phase with a receive clock signal phase based on receive clock signal phase data. A method includes storing a previous receive clock signal phase of a receiving channel and identifying a current receive clock signal phase of the receiving channel. The method further includes determining a phase difference between the previous receive clock signal phase and the current receive clock signal phase, and identifying a direction of the phase difference between the previous receive clock signal phase and the current receive clock signal phase. The method further includes adjusting a previous transmit clock signal phase of the transmitting channel to a current transmit clock signal phase of the transmitting channel based on the phase difference and direction.
摘要翻译：提出了用于使接收时钟信号相位与发送时钟信号相位同步的系统和方法。系统包括接收信道和发送信道，其中发送信道基于接收时钟信号相位数据将发送时钟信号相位与接收时钟信号相位同步。一种方法包括存储接收信道的先前接收时钟信号相位并识别接收信道的当前接收时钟信号相位。该方法还包括确定先前接收时钟信号相位与当前接收时钟信号相位之间的相位差，以及识别先前接收时钟信号相位与当前接收时钟信号相位之间的相位差的方向。该方法还包括基于相位差和方向将发送信道的先前发送时钟信号相位调整到发送信道的当前发送时钟信号相位。

10. 发明授权

US08532163B2 Method and transceiver system having a transmit clock signal phase that is phase-locked with a receive clock signal phase 有权
标题翻译：方法和收发机系统具有与接收时钟信号相锁相的发射时钟信号相位
公开(公告)号：US08532163B2
公开(公告)日：2013-09-10
申请号：US13367282
申请日：2012-02-06
申请人： Abbas Amirichimeh , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
发明人： Abbas Amirichimeh , Howard Baumer , John Louie , Vasudevan Parthasarathy , Linda Ying
IPC分类号： H04B1/38 , H04L7/00 , H03D3/24
CPC分类号： H03K5/135 , H04L7/0012 , H04L7/0091
摘要： A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.
摘要翻译：公开了一种收发器系统，其包括多个收发器芯片。每个收发器芯片包括一个或多个SERDES内核。每个SERDES核心包括一个或多个SERDES通道。每个SERDES通道包括接收通道和发送通道。每个SERDES通道的发送通道与相应的接收通道锁相。收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是一个不同的董事会。每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

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