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1. 发明授权

US08928425B1 Common mode detector for a communication system 有权
标题翻译：用于通信系统的共模检测器
公开(公告)号：US08928425B1
公开(公告)日：2015-01-06
申请号：US12604323
申请日：2009-10-22
申请人： Hossein Sedarat , Paul Langner , Ramin Farjadrad , Ramin Shirani
发明人： Hossein Sedarat , Paul Langner , Ramin Farjadrad , Ramin Shirani
IPC分类号： H03H7/00
CPC分类号： H04B3/32 , H01F19/04 , H04B3/30 , H04L25/0276 , H04L27/2647
摘要： A circuit for a wireline system is disclosed. In an embodiment, the circuit includes a twisted pair channel. The twisted pair channel delivers a differential signal that includes a converter mode component. The circuit includes at least one transformer coupled to the twisted pair channel and a transceiver coupled to the at least one transformer. The circuit further includes a common mode detection coupled to the transceiver for detecting a common mode component. In an embodiment, the circuit detects the common mode component. Accordingly, with common mode component detection capability, the common mode component of the differential can be analyzed for characterization purposes as well as for potential improvement in the system performance signal.
摘要翻译：公开了一种用于有线系统的电路。在一个实施例中，电路包括双绞线通道。双绞线通道提供包含转换器模式组件的差分信号。该电路包括耦合到双绞线信道的至少一个变压器和耦合到至少一个变压器的收发器。电路还包括耦合到收发器的共模检测用于检测共模分量。在一个实施例中，电路检测共模分量。因此，利用共模分量检测能力，可以分析差分的共模分量用于表征目的以及用于系统性能信号的潜在改进。

2. 发明授权

US08320411B1 Fast retraining for transceivers in communication systems 有权
标题翻译：快速再培训通信系统中的收发器
公开(公告)号：US08320411B1
公开(公告)日：2012-11-27
申请号：US12604358
申请日：2009-10-22
申请人： Hossein Sedarat , Paul Langner , Ramin Shirani , Ramin Farjadrad
发明人： Hossein Sedarat , Paul Langner , Ramin Shirani , Ramin Farjadrad
IPC分类号： H04J3/06 , G01R31/08 , H04L7/00
CPC分类号： H04W52/365
摘要： Fast retraining of communication parameters for a transceiver in a communication network. In one aspect, it is determined that the transceiver has lost the communication link for data communication, and the transceiver receives a signal providing a fast retraining sequence that updates transceiver parameters in order to reacquire the link for the data communication. The fast retraining sequence is performed in a reduced time relative to a full training sequence used for initializing the parameters for data communication by the transceiver.
摘要翻译：对通信网络中收发器的通信参数进行快速重新训练。在一个方面，确定收发器已经丢失了用于数据通信的通信链路，并且收发器接收提供快速再培训序列的信号，其更新收发器参数以便重新获取用于数据通信的链路。相对于用于初始化用于收发器的数据通信的参数的完整训练序列，在减少的时间内执行快速重新训练序列。

3. 发明授权

US08625704B1 Rejecting RF interference in communication systems 有权
标题翻译：拒绝通信系统中的射频干扰
公开(公告)号：US08625704B1
公开(公告)日：2014-01-07
申请号：US12604351
申请日：2009-10-22
申请人： Hossein Sedarat , Ramin Farjadrad , Ramin Shirani
发明人： Hossein Sedarat , Ramin Farjadrad , Ramin Shirani
IPC分类号： H04B15/00
CPC分类号： H04B3/32
摘要： Rejecting radio frequency (RF) interference in a communication system. In one aspect, rejecting RF interference includes receiving a signal on a signal path of a receiver from a communication channel, the signal including one or more received signal components having a frequency within a predetermined subset range of frequencies within an operating signal bandwidth of the receiver. The received signal components are attenuated using a notch filter to reduce RF interference obtained during transmission of the signal over the communication channel. In some embodiments, the one or more signal components have been boosted in power at a link partner transmitter connected to the communication channel.
摘要翻译：拒绝通信系统中的射频（RF）干扰。在一个方面，拒绝RF干扰包括从通信信道在接收机的信号路径上接收信号，所述信号包括一个或多个接收信号分量，所述接收信号分量具有在接收机的操作信号带宽内的预定子集范围内的频率。所接收的信号分量使用陷波滤波器衰减，以减少通过通信信道在信号传输期间获得的RF干扰。在一些实施例中，一个或多个信号分量在连接到通信信道的链路伙伴发射机处被提升。

4. 发明授权

US08284007B1 Magnetic package for a communication system 有权
标题翻译：用于通讯系统的磁性封装
公开(公告)号：US08284007B1
公开(公告)日：2012-10-09
申请号：US12604343
申请日：2009-10-22
申请人： Paul Langner , Ramin Farjadrad , Ramin Shirani , Jerry A. Martinson , Thomas Wayne Gandy
发明人： Paul Langner , Ramin Farjadrad , Ramin Shirani , Jerry A. Martinson , Thomas Wayne Gandy
IPC分类号： H01F21/02 , H01F27/28 , H04M9/08 , H04B3/28 , H04B3/00 , H04B1/00 , H03H7/00 , G01R15/18 , G01R19/22
CPC分类号： H04B3/32 , H01F19/04 , H04B3/30 , H04L25/0276 , H04L27/2647
摘要： A magnetic package for a communication system is disclosed the package comprises a plurality of transformers, wherein each transformer comprises a differential transformer. Each differential transformer comprises at least 2 sets of three pins. Each transformer is coupled to a twisted pair channel and a transceiver. The magnetic package includes at least one common mode transformer coupled to at least one of the transformers, wherein the at least one common mode transformer includes at least three pins. The at least three pins for the at least one common mode transformer are in a position relative to the other pins such that the package size is minimized.
摘要翻译：公开了一种用于通信系统的磁性封装，该封装包括多个变压器，其中每个变压器包括差动变压器。每个差分变压器包括至少2组三个引脚。每个变压器耦合到双绞线通道和收发器。磁性封装包括耦合到至少一个变压器的至少一个共模变压器，其中至少一个共模变压器包括至少三个引脚。用于至少一个共模变压器的至少三个引脚位于相对于另一个引脚的位置，使得封装尺寸最小化。

5. 发明授权

US07797613B1 Digital implementation of an enhanced minsum algorithm for error correction in data communications 有权
标题翻译：数字通信中用于纠错的增强型最小值算法的数字实现
公开(公告)号：US07797613B1
公开(公告)日：2010-09-14
申请号：US11678054
申请日：2007-02-22
申请人： Ramin Farjadrad , Ramin Shirani
发明人： Ramin Farjadrad , Ramin Shirani
IPC分类号： H03M13/45
CPC分类号： H03M13/112 , H03M13/15 , H03M13/1515 , H03M13/19 , H03M13/2957
摘要： An iterative error correcting decoder is provided. In one implementation, the iterative error correcting decoder includes an equality constraint node and a parity check node, the parity check node. The parity check node includes parity logic configured to receive input data bits from the equality constraint node and determine a first minimum value and a second minimum value associated with the input data bits using a MinSum algorithm. An enhancement function is performed on the first minimum value and the second minimum value. The enhancement function compares each of the first minimum value and the second minimum value with a first pre-determined constant value, and responsive to the first minimum value and the second minimum value being smaller than the first pre-determined constant value, the enhancement function passes the first minimum value and the second minimum value without any changes as output of the MinSum algorithm.
摘要翻译：提供了一种迭代纠错解码器。在一个实现中，迭代纠错解码器包括等式约束节点和奇偶校验节点，奇偶校验节点。奇偶校验节点包括奇偶校验逻辑，配置成从等式约束节点接收输入数据位，并使用MinSum算法确定与输入数据位相关联的第一最小值和第二最小值。对第一最小值和第二最小值执行增强功能。增强功能将第一最小值和第二最小值中的每一个与第一预定常数进行比较，并且响应于第一最小值和第二最小值小于第一预定常数值，增强函数将第一个最小值和第二个最小值作为MinSum算法的输出进行任何更改。

6. 发明授权

US07739558B1 Method and apparatus for rectifying errors in the presence of known trapping sets in iterative decoders and expedited bit error rate testing 有权
标题翻译：用于在迭代解码器中存在已知捕获集合的情况下纠正错误的方法和装置以及加速误码率测试
公开(公告)号：US07739558B1
公开(公告)日：2010-06-15
申请号：US11474158
申请日：2006-06-22
申请人： Ramin Farjadrad , Ramin Shirani
发明人： Ramin Farjadrad , Ramin Shirani
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H03M13/1142 , H03M13/015
摘要： A method and system for determining low error rate behavior of a device are provided. In one implementation, the method includes obtaining a dominant trapping set of a code, the dominant trapping set containing a plurality of variable nodes, and biasing bits associated with a programmable transmitter that is in communication with the device. The biased bits correspond to the variable nodes of the dominant trapping set. The method further includes transmitting random data from the programmable transmitter to the device, in which the random data includes one or more of the biased bits; measuring a number of error events corresponding to biased bits received by the device that cannot be decoded; and determining a true bit error rate of the device based on the measured number of error events.
摘要翻译：提供了一种用于确定设备的低错误率行为的方法和系统。在一个实现中，该方法包括获得代码的主要捕获集合，包含多个可变节点的主要陷阱集合以及与与该设备通信的可编程发射机相关联的偏置位。偏置位对应于主要捕获集合的可变节点。该方法还包括从可编程发射机向设备发送随机数据，其中随机数据包括偏置比特中的一个或多个; 测量与由所述设备接收的不能被解码的偏置位相对应的错误事件数; 以及基于所测量的错误事件数确定设备的真误码率。

7. 发明授权

US07577891B2 Method and apparatus for extending decoding time in an iterative decoder using input codeword pipelining 有权
标题翻译：用于使用输入码字流水线在迭代解码器中扩展解码时间的方法和装置
公开(公告)号：US07577891B2
公开(公告)日：2009-08-18
申请号：US11442485
申请日：2006-05-26
申请人： Ramin Farjadrad , Ramin Shirani
发明人： Ramin Farjadrad , Ramin Shirani
IPC分类号： H03M13/00
CPC分类号： H03M13/6597 , H03M13/1102 , H03M13/1105 , H03M13/2975 , H03M13/3738
摘要： A decoder architecture and method for implementing a decoder are provided. In one implementation, the decoder architecture includes an input buffer configured to receive a plurality of codewords to be processed, and includes an iterative decoder configured to receive a first codeword from the input buffer and process the first codeword. The iterative decoder processes the first codeword only for an amount of time required for the first codeword to become substantially error free. The decoder architecture further includes logic coupled to each of the iterative decoder and the input buffer. The logic is configured to determine when the first codeword processed by the decoder becomes substantially error free. The logic further generates a signal for loading a second codeword from the input buffer into the iterative decoder responsive to the logic determining when the first codeword becomes substantially error free.
摘要翻译：提供了一种用于实现解码器的解码器架构和方法。在一个实现中，解码器架构包括被配置为接收待处理的多个码字的输入缓冲器，并且包括被配置为从输入缓冲器接收第一码字并处理第一码字的迭代解码器。迭代解码器只处理第一码字所需的时间量变得基本上无差错的第一码字。解码器架构还包括耦合到每个迭代解码器和输入缓冲器的逻辑。逻辑被配置为确定由解码器处理的第一码字何时基本上无错误。该逻辑进一步产生用于将第二代码字从输入缓冲器加载到迭代解码器中的信号，该逻辑确定何时第一代码字基本上无错误。

8. 发明授权

US07528629B2 Low-power low-voltage multi-level variable-resistor line driver 有权
标题翻译：低功耗低压多电平可变电阻线路驱动器
公开(公告)号：US07528629B2
公开(公告)日：2009-05-05
申请号：US11198070
申请日：2005-08-04
申请人： Ramin Farjadrad , Ramin Shirani
发明人： Ramin Farjadrad , Ramin Shirani
IPC分类号： H03K19/094
CPC分类号： H04L25/028
摘要： A low-power multi-level pulse amplitude modulation (PAM) line driver using variable resistors for transmitting digital data over controlled-impedance transmission lines.
摘要翻译：低功耗多电平脉冲幅度调制（PAM）线路驱动器，使用可变电阻器通过受控阻抗传输线路传输数字数据。

9. 发明授权

US08234536B1 Iterative decoder using input data pipelining and time-interleaved processing 有权
标题翻译：迭代解码器采用输入数据流水线和时间交错处理
公开(公告)号：US08234536B1
公开(公告)日：2012-07-31
申请号：US12247833
申请日：2008-10-08
申请人： Ramin Farjadrad , Ramin Shirani
发明人： Ramin Farjadrad , Ramin Shirani
IPC分类号： H04L1/18
CPC分类号： H04L1/0052 , H03M13/1111 , H03M13/1145
摘要： In one implementation, a decoding architecture is provided that includes an input buffer configured to receive and store one or more codewords to be processed, and a decoder coupled to the input buffer. The decoder is configured to receive a first codeword and a second codeword from the input buffer, and simultaneously process the first codeword and the second codeword such that each of the first codeword and the second codeword is processed only for a minimum amount of time for the first codeword or the second codeword to become decoded. The input buffer is further configured to load a third codeword into the decoder responsive to the first codeword or the second codeword being decoded.
摘要翻译：在一个实现中，提供了一种解码架构，其包括被配置为接收和存储要处理的一个或多个码字的输入缓冲器，以及耦合到输入缓冲器的解码器。解码器被配置为从输入缓冲器接收第一码字和第二码字，并且同时处理第一码字和第二码字，使得第一码字和第二码字中的每一个仅处理最小量的时间第一码字或第二码字被解码。输入缓冲器还被配置为响应于正被解码的第一码字或第二码字而将第三码字加载到解码器中。

10. 发明授权

US08281210B1 Optimized correction factor for low-power min-sum low density parity check decoder (LDPC) 有权
标题翻译：低功耗最小和低密度奇偶校验解码器（LDPC）的优化校正因子
公开(公告)号：US08281210B1
公开(公告)日：2012-10-02
申请号：US12118650
申请日：2008-05-09
申请人： Ramin Farjadrad , Ramin Shirani
发明人： Ramin Farjadrad , Ramin Shirani
IPC分类号： H03M13/00
CPC分类号： H03M13/6583 , H03M13/112 , H03M13/1165 , H03M13/1191 , H03M13/6577
摘要： An iterative decoder configured to implement a min-sum with correction algorithm. The iterative decoder includes N parity check nodes coupled to M equality constraint nodes. The iterative decoder further includes a first parity check node configured to send an output to a first equality constraint node. Responsive to a minimum magnitude of other M−1 inputs to the first parity check node being lower than a pre-determined threshold, the parity check node sends the output having a same magnitude as that of the minimum magnitude of the other M−1 inputs to the first parity check node. Responsive to the minimum magnitude of the other M−1 inputs to the first parity check node being greater than the pre-determined threshold, the parity check node subtracts a correction factor in the form of p·2q from the minimum magnitude.
摘要翻译：配置为实现具有校正算法的最小和的迭代解码器。迭代解码器包括耦合到M个等式约束节点的N个奇偶校验节点。迭代解码器还包括被配置为将输出发送到第一等同约束节点的第一奇偶校验节点。响应于第一奇偶校验节点的其他M-1输入的最小幅度低于预定阈值，奇偶校验节点发送具有与其他M-1输入的最小幅值相同大小的输出到第一个奇偶校验节点。响应于第一奇偶校验节点的其他M-1输入的最小幅度大于预定阈值，奇偶校验节点从最小幅度减去p·2q形式的校正因子。

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