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1. 发明申请

US20120262228A1 CURRENT-MODE ANALOG BASEBAND APPARATUS 有权
标题翻译：电流模式基带设备
公开(公告)号：US20120262228A1
公开(公告)日：2012-10-18
申请号：US13530126
申请日：2012-06-22
申请人： Horng-Yuan Shih , Kai-Cheung Juang , Wei-Hsien Chen , Huan-Ke Chiu
发明人： Horng-Yuan Shih , Kai-Cheung Juang , Wei-Hsien Chen , Huan-Ke Chiu
IPC分类号： H04B15/00
CPC分类号： H04L25/0278
摘要： A current-mode analog baseband apparatus is provided. The apparatus includes a current-mode low-order filter, a current-mode programmable gain amplifier (PGA) unit and a high-order filter. The input impedance is smaller than the output impedance in the current-mode low-order filter. An input terminal of the current-mode PGA unit is connected to an output terminal of the current-mode low-order filter. An input terminal of the high-order filter is connected to an output terminal of the current-mode PGA unit.
摘要翻译：提供电流模式基带装置。该装置包括电流模式低阶滤波器，电流模式可编程增益放大器（PGA）单元和高阶滤波器。输入阻抗小于电流模式低阶滤波器的输出阻抗。电流模式PGA单元的输入端连接到当前模式低阶滤波器的输出端。高阶滤波器的输入端连接到电流模式PGA单元的输出端。

2. 发明申请

US20120019314A1 CURRENT-MODE ANALOG BASEBAND APPARATUS 有权
公开(公告)号：US20120019314A1
公开(公告)日：2012-01-26
申请号：US12855716
申请日：2010-08-13
申请人： Horng-Yuan Shih , Kai-Cheung Juang , Wei-Hsien Chen , Huan-Ke Chiu
发明人： Horng-Yuan Shih , Kai-Cheung Juang , Wei-Hsien Chen , Huan-Ke Chiu
IPC分类号： H04B15/00
CPC分类号： H04L25/0278
摘要： A current-mode analog baseband apparatus is provided. The apparatus includes a current-mode low-order filter, a current-mode programmable gain amplifier (PGA) unit and a high-order filter. The input impedance is smaller than the output impedance in the current-mode low-order filter. An input terminal of the current-mode PGA unit is connected to an output terminal of the current-mode low-order filter. An input terminal of the high-order filter is connected to an output terminal of the current-mode PGA unit.

3. 发明申请

US20110084863A1 PIPELINE TIME-TO-DIGITAL CONVERTER 有权
标题翻译：管道时间到数字转换器
公开(公告)号：US20110084863A1
公开(公告)日：2011-04-14
申请号：US12639003
申请日：2009-12-16
申请人： Huan-Ke Chiu , Horng-Yuan Shih , Chiou-Bang Chen , Tzu-Chan Chueh
发明人： Huan-Ke Chiu , Horng-Yuan Shih , Chiou-Bang Chen , Tzu-Chan Chueh
IPC分类号： H03M1/50 , H03M1/00
CPC分类号： G04F10/005
摘要： A pipeline time-to-digital converter (TDC) is provided. The pipeline TDC includes a plurality of TDC cells. Each of the TDC cells includes a delay unit, an output unit and a determination unit. The delay unit receives a first clock signal and a first reference signal output from a previous stage TDC cell. The delay unit generates sampling phases in a period between a trigger edge of the first reference signal and a trigger edge of the first clock signal, and samples the first clock signal to obtain sampling values in accordance with the sampling phases. The output unit calculates the sampling values for outputting a conversion value. The determination unit uses and analyses the sampling values and the sampling phases for outputting time residue to a next stage TDC cell.
摘要翻译：提供流水线时间数字转换器（TDC）。流水线TDC包括多个TDC单元。 TDC单元中的每一个包括延迟单元，输出单元和确定单元。延迟单元接收从前一级TDC单元输出的第一时钟信号和第一参考信号。延迟单元在第一参考信号的触发边沿和第一时钟信号的触发沿之间的周期内产生采样相位，并且对第一时钟信号进行采样以根据采样相位获得采样值。输出单元计算用于输出转换值的采样值。确定单元使用并分析用于将时间残差输出到下一级TDC单元的采样值和采样相位。

4. 发明授权

US07928888B1 Pipeline time-to-digital converter 有权
标题翻译：管道时间 - 数字转换器
公开(公告)号：US07928888B1
公开(公告)日：2011-04-19
申请号：US12639003
申请日：2009-12-16
申请人： Huan-Ke Chiu , Horng-Yuan Shih , Chiou-Bang Chen , Tzu-Chan Chueh
发明人： Huan-Ke Chiu , Horng-Yuan Shih , Chiou-Bang Chen , Tzu-Chan Chueh
IPC分类号： H03M1/38
CPC分类号： G04F10/005
摘要： A pipeline time-to-digital converter (TDC) is provided. The pipeline TDC includes a plurality of TDC cells. Each of the TDC cells includes a delay unit, an output unit and a determination unit. The delay unit receives a first clock signal and a first reference signal output from a previous stage TDC cell. The delay unit generates sampling phases in a period between a trigger edge of the first reference signal and a trigger edge of the first clock signal, and samples the first clock signal to obtain sampling values in accordance with the sampling phases. The output unit calculates the sampling values for outputting a conversion value. The determination unit uses and analyses the sampling values and the sampling phases for outputting time residue to a next stage TDC cell.
摘要翻译：提供流水线时间数字转换器（TDC）。流水线TDC包括多个TDC单元。 TDC单元中的每一个包括延迟单元，输出单元和确定单元。延迟单元接收从前一级TDC单元输出的第一时钟信号和第一参考信号。延迟单元在第一参考信号的触发边沿和第一时钟信号的触发沿之间的周期内产生采样相位，并且对第一时钟信号进行采样以根据采样相位获得采样值。输出单元计算用于输出转换值的采样值。确定单元使用并分析用于将时间残差输出到下一级TDC单元的采样值和采样相位。

5. 发明授权

US08058915B2 Digital phase-locked loop and digital phase-frequency detector thereof 有权
标题翻译：数字锁相环及其数字相位检波器
公开(公告)号：US08058915B2
公开(公告)日：2011-11-15
申请号：US12550393
申请日：2009-08-30
申请人： Huan-Ke Chiu , Tzu-Chan Chueh
发明人： Huan-Ke Chiu , Tzu-Chan Chueh
IPC分类号： H03L7/06 , H03D13/00
CPC分类号： H03L7/085 , H03D13/00 , H03L7/0802 , H03L7/087 , H03L7/093 , H03L2207/50
摘要： A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit, and a selector. The divisor switch unit receives and removes partial pulses of a feedback signal for obtaining a feedback clock. The low-resolution phase-error detecting unit detects phase error between a reference signal and the feedback clock to obtain a phase-error pulse width. The accumulating unit accumulates the feedback signal during the phase-error pulse width for obtaining an output selection signal. The high-resolution phase-error detecting unit detects phase error between the reference signal and the feedback signal to obtain a phase-error value. The constant unit provides at least one constant value. The selector selects and outputs one of the phase-error value and the constant value according to the output selection signal.
摘要翻译：提供数字锁相环及其数字相位检波器。数字PFD包括除数开关单元，低分辨率相位误差检测单元，累积单元，高分辨率相位误差检测单元，恒定单元和选择器。除数开关单元接收并去除用于获得反馈时钟的反馈信号的部分脉冲。低分辨率相位误差检测单元检测参考信号和反馈时钟之间的相位误差，以获得相位误差脉冲宽度。累加单元在相位误差脉冲宽度期间积累反馈信号以获得输出选择信号。高分辨率相位误差检测单元检测参考信号和反馈信号之间的相位误差，以获得相位误差值。恒定单位提供至少一个常数值。选择器根据输出选择信号选择并输出相位误差值和常数值之一。

6. 发明授权

US07940127B2 All digital phase lock loop and method for controlling phase lock loop 有权
标题翻译：所有数字锁相环和控制锁相环的方法
公开(公告)号：US07940127B2
公开(公告)日：2011-05-10
申请号：US12330100
申请日：2008-12-08
申请人： Huan-Ke Chiu , Chun-Jen Chen
发明人： Huan-Ke Chiu , Chun-Jen Chen
IPC分类号： H03L7/085
CPC分类号： H03L7/107 , H03L7/0991 , H03L7/10 , H03L7/1806 , H03L2207/50
摘要： An all digital phase lock loop is disclosed, including a digitally controlled oscillator, a phase detector, and a loop filter. The digitally controlled oscillator is controlled by an oscillator tuning word to generate a variable signal. The oscillator tuning word includes a first tuning word and a second tuning word, where the frequency range of the digitally controlled oscillator, capable to be adjusted by the second tuning word, is broader than that capable to be adjusted by the first tuning word. The phase detector detects a phase error between the variable signal and a reference signal. The phase error is received by the loop filter to output the oscillator tuning word. The loop filter has several stages of the low pass filters and a modification circuit. The modification circuit detects two filter outputs from two low pass filters among the filters and accordingly adjusts the second tuning word.
摘要翻译：公开了一种全数字锁相环，包括数字控制振荡器，相位检测器和环路滤波器。数字控制振荡器由振荡器调谐字控制，以产生可变信号。振荡器调谐字包括第一调谐字和第二调谐字，其中能够由第二调谐字调节的数字控制振荡器的频率范围比能够被第一调谐字调整的频率范围宽。相位检测器检测可变信号和参考信号之间的相位误差。相位误差由环路滤波器接收以输出振荡器调谐字。环路滤波器具有几级低通滤波器和修改电路。修改电路检测滤波器中的两个低通滤波器的两个滤波器输出，并相应地调整第二个调谐字。

7. 发明申请

US20100327912A1 DIGITAL PHASE-LOCKED LOOP AND DIGITAL PHASE-FREQUENCY DETECTOR THEREOF 有权
标题翻译：数字相位锁相环及其数字相位检波器
公开(公告)号：US20100327912A1
公开(公告)日：2010-12-30
申请号：US12550393
申请日：2009-08-30
申请人： Huan-Ke Chiu , Tzu-Chan Chueh
发明人： Huan-Ke Chiu , Tzu-Chan Chueh
IPC分类号： H03D13/00 , H03L7/06
CPC分类号： H03L7/085 , H03D13/00 , H03L7/0802 , H03L7/087 , H03L7/093 , H03L2207/50
摘要： A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit, and a selector. The divisor switch unit receives and removes partial pulses of a feedback signal for obtaining a feedback clock. The low-resolution phase-error detecting unit detects phase error between a reference signal and the feedback clock to obtain a phase-error pulse width. The accumulating unit accumulates the feedback signal during the phase-error pulse width for obtaining an output selection signal. The high-resolution phase-error detecting unit detects phase error between the reference signal and the feedback signal to obtain a phase-error value. The constant unit provides at least one constant value. The selector selects and outputs one of the phase-error value and the constant value according to the output selection signal.
摘要翻译：提供数字锁相环及其数字相位检波器。数字PFD包括除数开关单元，低分辨率相位误差检测单元，累积单元，高分辨率相位误差检测单元，恒定单元和选择器。除数开关单元接收并去除用于获得反馈时钟的反馈信号的部分脉冲。低分辨率相位误差检测单元检测参考信号和反馈时钟之间的相位误差，以获得相位误差脉冲宽度。累加单元在相位误差脉冲宽度期间积累反馈信号以获得输出选择信号。高分辨率相位误差检测单元检测参考信号和反馈信号之间的相位误差，以获得相位误差值。恒定单位提供至少一个常数值。选择器根据输出选择信号选择并输出相位误差值和常数值之一。

8. 发明申请

US20130156135A1 I/Q DEMODULATION APPARATUS AND METHOD WITH PHASE SCANNING 有权
标题翻译： I / Q解调装置和相位扫描方法
公开(公告)号：US20130156135A1
公开(公告)日：2013-06-20
申请号：US13396603
申请日：2012-02-15
申请人： Huan-Ke Chiu , Jia-Hung Peng
发明人： Huan-Ke Chiu , Jia-Hung Peng
IPC分类号： H04L27/06
CPC分类号： H04L27/38
摘要： An I/Q demodulation apparatus and method with phase scanning are provided. The demodulation apparatus includes a ring oscillator, a first latch unit, a decoding unit, a counter unit, a second latch unit, a first arithmetical unit and a second arithmetical unit. The first latch unit samples phase signals outputted from the ring oscillator. The decoding unit decodes the output of the first latch unit to correspondingly generate fine code of a first, a second, a third and a fourth codes. The counter unit counts the phase signals. The second latch unit samples the output of the counter unit to correspondingly generate coarse code of the first, the second, the third and the fourth codes. The first arithmetical unit performs an addition/subtraction operation by using the first code and the second code. The second arithmetical unit performs the addition/subtraction operation by using the third code and the fourth code.
摘要翻译：提供了具有相位扫描的I / Q解调装置和方法。解调装置包括环形振荡器，第一锁存单元，解码单元，计数器单元，第二锁存单元，第一算术单元和第二算术单元。第一锁存单元对从环形振荡器输出的相位信号进行采样。解码单元对第一锁存单元的输出进行解码，以对应地生成第一，第二，第三和第四代码的精细代码。计数器单元对相位信号进行计数。第二锁存单元对计数器单元的输出进行采样，以对应地生成第一，第二，第三和第四代码的粗略代码。第一算术单元通过使用第一代码和第二代码执行加法/减法操作。第二算术单元通过使用第三代码和第四代码执行加法/减法运算。

9. 发明申请

US20100120381A1 POLAR TRANSMITTER, METHOD AND APPARATUS FOR PHASE MODULATION 有权
标题翻译：极性发射器，相位调制的方法和装置
公开(公告)号：US20100120381A1
公开(公告)日：2010-05-13
申请号：US12436016
申请日：2009-05-05
申请人： Huan-Ke Chiu , Chun-Jen Chen
发明人： Huan-Ke Chiu , Chun-Jen Chen
IPC分类号： H04B1/04
CPC分类号： H03C5/00
摘要： A phase modulation method with a polar transmitter. A target frequency is first designated by comparing the RF signal with a reference frequency and the phase sample. An oscillator control word is generated based on the target frequency. A digital oscillator can modulate from a first phase to a second phase to synthesize a preliminary RF signal based on the oscillator control word. When the target frequency exceeds the modulation capability of the digital oscillator, the oscillator control word is generated based on the target frequency minus 180 degrees, and the preliminary RF signal is shifted by 180 degrees to be the RF signal having the target frequency. When the target frequency does not exceed the modulation capability of the digital oscillator, the oscillator control word is generated solely based on the target frequency to output the preliminary RF signal to be the RF signal having the target frequency.
摘要翻译：一种带极性发射机的相位调制方法。首先通过将RF信号与参考频率和相位采样进行比较来指定目标频率。基于目标频率产生振荡器控制字。数字振荡器可以从第一相位调制到第二相位，以基于振荡器控制字来合成初步RF信号。当目标频率超过数字振荡器的调制能力时，基于目标频率减去180度产生振荡器控制字，并将初步RF信号偏移180度作为具有目标频率的RF信号。当目标频率不超过数字振荡器的调制能力时，仅基于目标频率产生振荡器控制字，以将初步RF信号输出为具有目标频率的RF信号。

10. 发明授权

US07620140B2 Programmable integer and fractional frequency divider 有权
$Programmable integer and fractional frequency divider$
公开(公告)号：US07620140B2
公开(公告)日：2009-11-17
申请号：US12354719
申请日：2009-01-15
申请人： Huan-Ke Chiu , Yeong-Lin Yu , Tzu-Yi Yang
发明人： Huan-Ke Chiu , Yeong-Lin Yu , Tzu-Yi Yang
IPC分类号： H03K21/00 , H03K23/00
CPC分类号： H03K23/68 , H03K23/667
摘要： A programmable integer and fractional frequency divider is provided. The programmable divider divides a frequency of an input signal by a first divisor to generate an output signal, and comprises a programmable integer frequency divider and a fractional number switch. The programmable integer frequency divider divides the frequency of the input signal by a second divisor to generate the output signal, wherein the second divisor is first or second integers depending on a divisor switching signal. The fractional number switch calculates a pulse count of the output signal, and generates the divisor switching signal to switch from the first to the second integer when the pulse count of the output signal equals to a predetermined pulse count determined by a fractional part of the first divisor, and receives a fractional divisor control signal to change the predetermined pulse count, thereby changing the fractional part of the first divisor.

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