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1. 发明授权

US08078835B2 Reconfigurable array processor for floating-point operations 有权
标题翻译：用于浮点运算的可重构阵列处理器
公开(公告)号：US08078835B2
公开(公告)日：2011-12-13
申请号：US12126825
申请日：2008-05-23
申请人： Hoon Mo Yang , Man Hwee Jo , Il Hyun Park , Ki Young Choi
发明人： Hoon Mo Yang , Man Hwee Jo , Il Hyun Park , Ki Young Choi
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F7/57 , G06F2207/3824
摘要： A processor for performing floating-point operations includes an array of processing elements arranged to enable a floating-point operation. Each processing element includes an arithmetic logic unit to receive two input values and perform integer arithmetic on the received input values. The processing elements in the array are connected together in groups of two or more processing elements to enable floating-point operation.
摘要翻译：用于执行浮点运算的处理器包括布置成启用浮点运算的处理元件阵列。每个处理元件包括用于接收两个输入值并对接收的输入值执行整数运算的算术逻辑单元。阵列中的处理元件以两个或多个处理元件的组连接在一起，以实现浮点运算。

2. 发明授权

US08046564B2 Reconfigurable paired processing element array configured with context generated each cycle by FSM controller for multi-cycle floating point operation 失效
标题翻译：可配置的配对处理元件阵列配置有上下文，由FSM控制器为每个周期生成多周期浮点运算
公开(公告)号：US08046564B2
公开(公告)日：2011-10-25
申请号：US12234507
申请日：2008-09-19
申请人： Hoon Mo Yang , Man Hwee Jo , Il Hyun Park , Ki Young Choi
发明人： Hoon Mo Yang , Man Hwee Jo , Il Hyun Park , Ki Young Choi
IPC分类号： G06F9/302
CPC分类号： G06F7/483 , G06F7/575 , G06F15/7867 , G06F2207/3896
摘要： Techniques, systems and apparatus are described for providing a processing element (PE) structure forming a floating point unit (FPU)-processing element. Each processing element includes each of two multiplexers (MUXes) to receive data from one or more sources including another PE, and select one value from the received data. The processing element includes an arithmetic logic unit (ALU) in communication with the two multiplexers to receive the selected value from each multiplexer as two input values, and process the received two input values to generate results of the ALU.
摘要翻译：描述了用于提供形成浮点单元（FPU）处理元件的处理元件（PE）结构的技术，系统和装置。每个处理元件包括从包括另一个PE的一个或多个源接收数据的两个多路复用器（MUX）中的每一个，并从接收到的数据中选择一个值。处理元件包括与两个多路复用器通信的算术逻辑单元（ALU），以从每个多路复用器接收所选择的值作为两个输入值，并且处理所接收的两个输入值以生成ALU的结果。

3. 发明申请

US20090113169A1 RECONFIGURABLE ARRAY PROCESSOR FOR FLOATING-POINT OPERATIONS 有权
标题翻译：用于浮点操作的可重构阵列处理器
公开(公告)号：US20090113169A1
公开(公告)日：2009-04-30
申请号：US12126825
申请日：2008-05-23
申请人： Hoon Mo Yang , Man Hwee Jo , IL Hyun Park , Ki Young Choi
发明人： Hoon Mo Yang , Man Hwee Jo , IL Hyun Park , Ki Young Choi
IPC分类号： G06F9/302 , G06F15/80 , G06F9/06
CPC分类号： G06F7/57 , G06F2207/3824
摘要： A processor for performing floating-point operations includes an array of processing elements arranged to enable a floating-point operation. Each processing element includes an arithmetic logic unit to receive two input values and perform integer arithmetic on the received input values. The processing elements in the array are connected together in groups of two or more processing elements to enable floating-point operation.
摘要翻译：用于执行浮点运算的处理器包括布置成启用浮点运算的处理元件阵列。每个处理元件包括一个算术逻辑单元，用于接收两个输入值，并对接收到的输入值执行整数运算。阵列中的处理元件以两个或多个处理元件的组连接在一起，以实现浮点运算。

4. 发明申请

US20090083519A1 Processing Element (PE) Structure Forming Floating Point-Reconfigurable Array (FP-RA) and FP-RA Control Circuit for Controlling the FP-RA 失效
标题翻译：处理元件（PE）结构形成用于控制FP-RA的浮点可重构阵列（FP-RA）和FP-RA控制电路
公开(公告)号：US20090083519A1
公开(公告)日：2009-03-26
申请号：US12234507
申请日：2008-09-19
申请人： Hoon Mo Yang , Man Hwee Jo , Il Hyun Park , Ki Young Choi
发明人： Hoon Mo Yang , Man Hwee Jo , Il Hyun Park , Ki Young Choi
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F7/483 , G06F7/575 , G06F15/7867 , G06F2207/3896
摘要： Techniques, systems and apparatus are described for providing a processing element (PE) structure forming a floating point unit (FPU)-processing element. Each processing element includes each of two multiplexers (MUXes) to receive data from one or more sources including another PE, and select one value from the received data. The processing element includes an arithmetic logic unit (ALU) in communication with the two multiplexers to receive the selected value from each multiplexer as two input values, and process the received two input values to generate results of the ALU.
摘要翻译：描述了用于提供形成浮点单元（FPU）处理元件的处理元件（PE）结构的技术，系统和装置。每个处理元件包括从包括另一个PE的一个或多个源接收数据的两个多路复用器（MUX）中的每一个，并从接收到的数据中选择一个值。处理元件包括与两个多路复用器通信的算术逻辑单元（ALU），以从每个多路复用器接收所选择的值作为两个输入值，并且处理所接收的两个输入值以生成ALU的结果。

5. 发明授权

US08089379B2 Variable length decoding apparatus and method 失效
标题翻译：可变长度解码装置及方法
公开(公告)号：US08089379B2
公开(公告)日：2012-01-03
申请号：US12635558
申请日：2009-12-10
申请人： Ki Wook Yoon , Venkata Krishna Prasad Arava , Ki Young Choi , Man Hwee Jo , Hyouk Joong Lee
发明人： Ki Wook Yoon , Venkata Krishna Prasad Arava , Ki Young Choi , Man Hwee Jo , Hyouk Joong Lee
IPC分类号： H03M7/40
CPC分类号： H03M7/425
摘要： Techniques, apparatus and systems are described for performing variable length decoding. In one aspect, a variable length decoding apparatus includes a first computation unit to determine whether a symbol corresponding to an input data is included in an upper group or a lower group of a variable length code tree. Responsive to the determination, when the symbol corresponding to the input data is included in the lower group, the first computation unit detects look-up table information corresponding to a subgroup that includes the symbol corresponding to the input data within the lower group that includes multiple subgroups. The variable length decoding apparatus includes a second computation unit to detect the symbol corresponding to the input data by searching a look-up table corresponding to the look-up table information when the look-up table information is received from the first computation unit.
摘要翻译：描述了用于执行可变长度解码的技术，装置和系统。一方面，可变长度解码装置包括：第一计算单元，用于确定与输入数据相对应的符号是否包括在可变长度码树的上组或下组中。响应于确定，当对应于输入数据的符号被包括在下组中时，第一计算单元检测与包括与包括多个的下组中的输入数据相对应的符号的子组相对应的查找表信息子组。可变长度解码装置包括第二计算单元，用于当从第一计算单元接收到查找表信息时，通过搜索与查找表信息相对应的查找表来检测与输入数据相对应的符号。

6. 发明申请

US20100149005A1 VARIABLE LENGTH DECODING APPARATUS AND METHOD 失效
标题翻译：可变长度解码装置和方法
公开(公告)号：US20100149005A1
公开(公告)日：2010-06-17
申请号：US12635558
申请日：2009-12-10
申请人： Ki Wook Yoon , Venkata Krishna Prasad Arava , Ki Young Choi , Man Hwee Jo , Hyouk Joong Lee
发明人： Ki Wook Yoon , Venkata Krishna Prasad Arava , Ki Young Choi , Man Hwee Jo , Hyouk Joong Lee
IPC分类号： H03M7/40
CPC分类号： H03M7/425
摘要： Techniques, apparatus and systems are described for performing variable length decoding. In one aspect, a variable length decoding apparatus includes a first computation unit to determine whether a symbol corresponding to an input data is included in an upper group or a lower group of a variable length code tree. Responsive to the determination, when the symbol corresponding to the input data is included in the lower group, the first computation unit detects look-up table information corresponding to a subgroup that includes the symbol corresponding to the input data within the lower group that includes multiple subgroups. The variable length decoding apparatus includes a second computation unit to detect the symbol corresponding to the input data by searching a look-up table corresponding to the look-up table information when the look-up table information is received from the first computation unit.
摘要翻译：描述了用于执行可变长度解码的技术，装置和系统。一方面，可变长度解码装置包括：第一计算单元，用于确定与输入数据相对应的符号是否包括在可变长度码树的上组或下组中。响应于确定，当对应于输入数据的符号被包括在下组中时，第一计算单元检测与包括与包括多个的下组中的输入数据相对应的符号的子组相对应的查找表信息子组。可变长度解码装置包括第二计算单元，用于当从第一计算单元接收到查找表信息时，通过搜索与查找表信息相对应的查找表来检测与输入数据相对应的符号。

7. 发明申请

US20100088687A1 Variable Length Code Table Clustering Method, and Method and Apparatus for Sharing Memory of Multi-Codec by Using the Variable Length Code Table Clustering Method 审中-公开
标题翻译：可变长度代码表聚类方法，以及通过使用可变长度代码表共享方法来共享多编解码器的存储器的方法和装置
公开(公告)号：US20100088687A1
公开(公告)日：2010-04-08
申请号：US12420633
申请日：2009-04-08
申请人： Ki Young Choi , Venkata Krishna Prasad Arava , Ki Wook Yoon , Hyouk Joong Lee , Man Hwee Jo
发明人： Ki Young Choi , Venkata Krishna Prasad Arava , Ki Wook Yoon , Hyouk Joong Lee , Man Hwee Jo
IPC分类号： G06F9/45 , G06F12/00 , G06F12/02
CPC分类号： H04N19/436 , H04N19/13 , H04N19/423 , H04N19/61
摘要： Provided are a method and apparatus for sharing a memory of a multi-codec. For each of a plurality of codecs, the method and apparatus cluster a variable length code tree into a plurality of groups whereby a level difference between symbols in each group of the plurality of groups is less than a predetermined value, wherein the variable length code tree corresponds to at least one of variable length code tables for each of the plurality of codecs, refer to maximum levels of the symbols in each group of the plurality of groups, and determine a storage capacity of an internal memory shared between the variable length code tables for the plurality of codecs.
摘要翻译：提供了一种用于共享多编解码器的存储器的方法和装置。对于多个编解码器中的每一个，所述方法和装置将可变长度代码树聚类成多个组，由此多个组中的每个组中的符号之间的电平差小于预定值，其中可变长度代码树对应于多个编解码器中的每一个的可变长度代码表中的至少一个，参考多个组中的每个组中的符号的最大级别，并且确定在可变长度代码表之间共享的内部存储器的存储容量用于多个编解码器。

8. 发明授权

US08949550B2 Memory-centered communication apparatus in a coarse grained reconfigurable array 有权
标题翻译：以粗粒度重构阵列为基础的以内存为中心的通讯装置
公开(公告)号：US08949550B2
公开(公告)日：2015-02-03
申请号：US13635620
申请日：2010-06-01
申请人： Ki Young Choi , Kyung Wook Chang , Jong Kyung Paek
发明人： Ki Young Choi , Kyung Wook Chang , Jong Kyung Paek
IPC分类号： G06F12/08 , G06F13/00 , G06F15/78
CPC分类号： G06F15/7871
摘要： The present invention relates to a coarse-grained reconfigurable array, comprising: at least one processor; a processing element array including a plurality of processing elements, and a configuration cache where commands being executed by the processing elements are saved; and a plurality of memory units forming a one-to-one mapping with the processor and the processing element array. The coarse-grained reconfigurable array further comprises a central memory performing data communications between the processor and the processing element array by switching the one-to-one mapping such that when the processor transfers data from/to a main memory to/from a frame buffer, a significant bottleneck phenomenon that may occur due to the limited bandwidth and latency of a system bus can be improved.
摘要翻译：本发明涉及一种粗粒度可重构阵列，包括：至少一个处理器; 包括多个处理元件的处理元件阵列，以及由处理元件执行命令的配置高速缓存; 以及与处理器和处理元件阵列形成一对一映射的多个存储器单元。粗粒度可重配置阵列还包括通过切换一对一映射来执行处理器和处理元件阵列之间的数据通信的中央存储器，使得当处理器从/从帧缓冲器向/从主存储器传送数据可以提高由于系统总线的有限带宽和延迟而可能发生的显着的瓶颈现象。

9. 发明申请

US20130024621A1 MEMORY-CENTERED COMMUNICATION APPARATUS IN A COARSE GRAINED RECONFIGURABLE ARRAY 有权
标题翻译：一个粗糙的可重新配置的阵列中的记忆中心通信设备
公开(公告)号：US20130024621A1
公开(公告)日：2013-01-24
申请号：US13635620
申请日：2010-06-01
申请人： Ki Young Choi , Kyung Wook Chang , Jong Kyung Paek
发明人： Ki Young Choi , Kyung Wook Chang , Jong Kyung Paek
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F15/7871
摘要： The present invention relates to a coarse-grained reconfigurable array, comprising: at least one processor; a processing element array including a plurality of processing elements, and a configuration cache where commands being executed by the processing elements are saved; and a plurality of memory units forming a one-to-one mapping with the processor and the processing element array. The coarse-grained reconfigurable array further comprises a central memory performing data communications between the processor and the processing element array by switching the one-to-one mapping such that when the processor transfers data from/to a main memory to/from a frame buffer, a significant bottleneck phenomenon that may occur due to the limited bandwidth and latency of a system bus can be improved.
摘要翻译：本发明涉及一种粗粒度可重构阵列，包括：至少一个处理器; 包括多个处理元件的处理元件阵列，以及由处理元件执行命令的配置高速缓存; 以及与处理器和处理元件阵列形成一对一映射的多个存储器单元。粗粒度可重配置阵列还包括通过切换一对一映射来执行处理器和处理元件阵列之间的数据通信的中央存储器，使得当处理器从/从帧缓冲器向/从主存储器传送数据可以提高由于系统总线的有限带宽和延迟而可能发生的显着的瓶颈现象。

10. 发明授权

US06707491B1 Method of correcting white balance in video camera 有权
标题翻译：校正摄像机白平衡的方法
公开(公告)号：US06707491B1
公开(公告)日：2004-03-16
申请号：US09379326
申请日：1999-08-23
申请人： Ki Young Choi
发明人： Ki Young Choi
IPC分类号： H04N973
CPC分类号： H04N9/735
摘要： A method of correcting white balance in a video camera is provided, which controls the red gain and blue gain of a captured image signal to allow the average of color difference signals of a picture, the method including the steps of (a) dividing the captured image of one picture into a predetermined number of unit cells, and accumulating the color difference signals by cells divided, (b) extracting an effective cell according as the accumulated data of each of the unit cells is data required for white balance correction or not, (c) judging whether data of the effective cell extracted in step (b) is monochrome data or mixed color data, (d) performing white balance correction without using the effective cell when the data of the effective cell is judged to be mixed color data in step (c), and (e) carrying out white balance correction using the effective cell when the data of the effective cell is judged to be monochrome data in step (c).
摘要翻译：提供了一种校正摄像机中的白平衡的方法，其控制拍摄图像信号的红增益和蓝增益以允许图像的色差信号的平均值，该方法包括以下步骤：（a）一个图像的图像到预定数量的单位单元中，并且通过被分割的单元累积色差信号，（b）根据每个单位单元的累积数据提取有效单元是白平衡校正所需要的数据，（c）判断在步骤（b）中提取的有效单元的数据是单色数据还是混合颜色数据，（d）当有效单元的数据被判定为混合颜色数据时，（d）执行白平衡校正而不使用有效单元在步骤（c）中，和（e）在步骤（c）中当有效单元的数据被判断为单色数据时，使用有效单元进行白平衡校正。

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