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1. 发明申请

US20100057471A1 METHOD AND SYSTEM FOR PROCESSING AUDIO SIGNALS VIA SEPARATE INPUT AND OUTPUT PROCESSING PATHS 审中-公开
标题翻译：通过分离输入和输出处理程序处理音频信号的方法和系统
公开(公告)号：US20100057471A1
公开(公告)日：2010-03-04
申请号：US12248426
申请日：2008-10-09
申请人： Hongwei Kong , Nelson Sollenberger , Taiyi Cheng , Mark Hahm , Todd L. Brooks , Xicheng Jiang
发明人： Hongwei Kong , Nelson Sollenberger , Taiyi Cheng , Mark Hahm , Todd L. Brooks , Xicheng Jiang
IPC分类号： G10L19/00
CPC分类号： H04M1/6025 , H04R1/1091 , H04R25/554 , H04R27/00 , H04R2227/003 , H04R2420/07
摘要： Aspects of a method and system for processing audio signals via separate input and output processing paths are provided. In this regard, a hardware audio CODEC comprising one or more audio inputs and one or more audio outputs and may be enabled to route, via one or more switching elements, audio signals from any of the inputs to any of the outputs. The CODEC may be enabled to simultaneously process a plurality of audio signals based on a configuration of the switching elements. Upstream from the switching elements, received audio signals may be processed independent of an output to which the may be communicated. Downstream from said switching elements audio signals may be processed independent of an input via which the signals were received.
摘要翻译：提供了通过单独的输入和输出处理路径处理音频信号的方法和系统的方面。在这方面，包括一个或多个音频输入和一个或多个音频输出的硬件音频编解码器，并且可以使得能够经由一个或多个开关元件将来自任何输入的音频信号路由到任何输出。可以使CODEC可以基于开关元件的配置来同时处理多个音频信号。从开关元件的上游，接收的音频信号可以独立于可以被传送到的输出进行处理。来自所述开关元件的下游音频信号可以独立于接收信号的输入进行处理。

2. 发明授权

US08284819B2 Method and system for interference suppression in WCDMA systems 有权
标题翻译： WCDMA系统干扰抑制方法与系统
公开(公告)号：US08284819B2
公开(公告)日：2012-10-09
申请号：US12582771
申请日：2009-10-21
申请人： Mark Hahm , Wei Luo , Arkady Molev-Shteiman , Hongwei Kong , Xiao-Feng Qi , Li Fung Chang , Nelson Sollenberger
发明人： Mark Hahm , Wei Luo , Arkady Molev-Shteiman , Hongwei Kong , Xiao-Feng Qi , Li Fung Chang , Nelson Sollenberger
IPC分类号： H04B1/00
CPC分类号： H04B1/712 , H04J11/0063 , H04J13/0044 , H04J13/0048
摘要： Aspects of a method and system for interference suppression in WCDMA systems may include one or more circuits that are operable to receive a plurality of multipath signals via one or more receiving antennas. A plurality of weighting factor values may be computed based on the received multipath signals. Estimated signals may be based on the weighting factor values. Residual signals may be generated based on received signals and the estimated signals. Addback signals may be generated based on the estimated signals and the residual signals. Updated estimated signals may be generated based on the addback signals and the weighting factor values. Incremental signals may be generated based on the updated estimated signals and addback signals. Updated residual signals may be generated based on the incremental signals and previous residual signals. The interference suppressed signals may be generated based on the updated residual signals and updated estimated signals.
摘要翻译：用于WCDMA系统中的干扰抑制的方法和系统的方面可以包括可操作以经由一个或多个接收天线接收多个多径信号的一个或多个电路。可以基于接收的多路径信号来计算多个加权因子值。估计信号可以基于加权因子值。可以基于接收的信号和估计的信号来产生残余信号。可以基于估计的信号和残留信号来生成附加信号。可以基于附加信号和加权因子值来生成更新的估计信号。可以基于更新的估计信号和加法信号来产生增量信号。可以基于增量信号和先前的剩余信号来生成更新的残留信号。可以基于更新的残差信号和更新的估计信号来产生干扰抑制信号。

3. 发明授权

US08503506B2 Method and system for interference suppression in WCDMA systems 有权
标题翻译： WCDMA系统干扰抑制方法与系统
公开(公告)号：US08503506B2
公开(公告)日：2013-08-06
申请号：US13588297
申请日：2012-08-17
申请人： Mark Hahm , Wei Luo , Arkady Molev-Shteiman , Hongwei Kong , Xiao-Feng Qi , Li Fung Chang , Nelson Sollenberger
发明人： Mark Hahm , Wei Luo , Arkady Molev-Shteiman , Hongwei Kong , Xiao-Feng Qi , Li Fung Chang , Nelson Sollenberger
IPC分类号： H04B1/707
CPC分类号： H04B1/712 , H04J11/0063 , H04J13/0044 , H04J13/0048
摘要： Aspects of a method and system for interference suppression in WCDMA systems may include one or more circuits that are operable to receive a plurality of multipath signals via one or more receiving antennas. A plurality of weighting factor values may be computed based on the received multipath signals. Estimated signals may be based on the weighting factor values. Residual signals may be generated based on received signals and the estimated signals. Addback signals may be generated based on the estimated signals and the residual signals. Updated estimated signals may be generated based on the addback signals and the weighting factor values. Incremental signals may be generated based on the updated estimated signals and addback signals. Updated residual signals may be generated based on the incremental signals and previous residual signals. The interference suppressed signals may be generated based on the updated residual signals and updated estimated signals.
摘要翻译：用于WCDMA系统中的干扰抑制的方法和系统的方面可以包括可操作以经由一个或多个接收天线接收多个多径信号的一个或多个电路。可以基于接收的多路径信号来计算多个加权因子值。估计信号可以基于加权因子值。可以基于接收的信号和估计的信号来产生残余信号。可以基于估计的信号和残留信号来生成附加信号。可以基于附加信号和加权因子值来生成更新的估计信号。可以基于更新的估计信号和加法信号来产生增量信号。可以基于增量信号和先前的剩余信号来生成更新的残留信号。可以基于更新的残差信号和更新的估计信号来产生干扰抑制信号。

4. 发明申请

US20080132190A1 Method and system for delay matching in a rake receiver 有权
标题翻译：耙式接收机延时匹配的方法和系统
公开(公告)号：US20080132190A1
公开(公告)日：2008-06-05
申请号：US11607438
申请日：2006-12-01
申请人： Hongwei Kong , Nelson Sollenberger , Li Fung Chang , Zoran Kostic , Mark Hahm
发明人： Hongwei Kong , Nelson Sollenberger , Li Fung Chang , Zoran Kostic , Mark Hahm
IPC分类号： H04B1/10
CPC分类号： H04B1/7115 , H04B1/7117 , H04B2201/70701
摘要： Certain aspects of a method and system for delay matching in a rake receiver are disclosed. Aspects of one method may include compensating for a delay associated with at least one or both of the following in a rake receiver: a control channel and a data channel, prior to individual processing of received data by the data channel and individual processing of received data by the control channel. The data channel or the dedicated physical channel (DPCH) may be delayed with respect to the control channel, which may comprise, for example, the common pilot control channel (CPICH), by a particular time period.
摘要翻译：公开了用于耙式接收机中的延迟匹配的方法和系统的某些方面。一种方法的方面可以包括在耙式接收机中补偿与以下中的至少一个或两者相关联的延迟：控制信道和数据信道，在数据信道对接收到的数据进行单独处理之前，以及接收数据的单独处理由控制通道。数据信道或专用物理信道（DPCH）可以相对于可以包括例如公共导频控制信道（CPICH）的控制信道延迟特定时间段。

5. 发明授权

US08831139B2 Method and system for delay matching in a rake receiver 有权
标题翻译：耙式接收机延时匹配的方法和系统
公开(公告)号：US08831139B2
公开(公告)日：2014-09-09
申请号：US11607438
申请日：2006-12-01
申请人： Hongwei Kong , Nelson Sollenberger , Li Fung Chang , Zoran Kostic , Mark Hahm
发明人： Hongwei Kong , Nelson Sollenberger , Li Fung Chang , Zoran Kostic , Mark Hahm
IPC分类号： H04B1/10 , H04B1/7115 , H04B1/7117
CPC分类号： H04B1/7115 , H04B1/7117 , H04B2201/70701
摘要： Certain aspects of a method and system for delay matching in a rake receiver are disclosed. Aspects of one method may include compensating for a delay associated with at least one or both of the following in a rake receiver: a control channel and a data channel, prior to individual processing of received data by the data channel and individual processing of received data by the control channel. The data channel or the dedicated physical channel (DPCH) may be delayed with respect to the control channel, which may comprise, for example, the common pilot control channel (CPICH), by a particular time period.
摘要翻译：公开了用于耙式接收机中的延迟匹配的方法和系统的某些方面。一种方法的方面可以包括在耙式接收机中补偿与以下中的至少一个或两者相关联的延迟：控制信道和数据信道，在数据信道对接收到的数据进行单独处理之前，以及接收数据的单独处理由控制通道。数据信道或专用物理信道（DPCH）可以相对于可以包括例如公共导频控制信道（CPICH）的控制信道延迟特定时间段。

6. 发明申请

US20110090996A1 METHOD AND SYSTEM FOR INTERFERENCE SUPPRESSION IN WCDMA SYSTEMS 有权
标题翻译： WCDMA系统干扰抑制方法与系统
公开(公告)号：US20110090996A1
公开(公告)日：2011-04-21
申请号：US12582771
申请日：2009-10-21
申请人： Mark Hahm , Wei Luo , Arkady Molev-Shteiman , Hongwei Kong , Xiao-Feng Qi , Li Fung Chang , Nelson Sollenberger
发明人： Mark Hahm , Wei Luo , Arkady Molev-Shteiman , Hongwei Kong , Xiao-Feng Qi , Li Fung Chang , Nelson Sollenberger
IPC分类号： H04L1/02
CPC分类号： H04B1/712 , H04J11/0063 , H04J13/0044 , H04J13/0048
摘要： Aspects of a method and system for interference suppression in WCDMA systems may include one or more circuits that are operable to receive a plurality of multipath signals via one or more receiving antennas. A plurality of weighting factor values may be computed based on the received multipath signals. Estimated signals may be based on the weighting factor values. Residual signals may be generated based on received signals and the estimated signals. Addback signals may be generated based on the estimated signals and the residual signals. Updated estimated signals may be generated based on the addback signals and the weighting factor values. Incremental signals may be generated based on the updated estimated signals and addback signals. Updated residual signals may be generated based on the incremental signals and previous residual signals. The interference suppressed signals may be generated based on the updated residual signals and updated estimated signals.
摘要翻译：用于WCDMA系统中的干扰抑制的方法和系统的方面可以包括可操作以经由一个或多个接收天线接收多个多径信号的一个或多个电路。可以基于接收的多路径信号来计算多个加权因子值。估计信号可以基于加权因子值。可以基于接收的信号和估计的信号来产生残余信号。可以基于所估计的信号和残留信号来生成附加信号。可以基于附加信号和加权因子值来生成更新的估计信号。可以基于更新的估计信号和加法信号来产生增量信号。可以基于增量信号和先前的剩余信号来生成更新的残留信号。可以基于更新的残差信号和更新的估计信号来产生干扰抑制信号。

7. 发明申请

US20070188503A1 Method and system for programmable breakpoints in an integrated embedded image and video accelerator 有权
标题翻译：集成嵌入式图像和视频加速器中可编程断点的方法和系统
公开(公告)号：US20070188503A1
公开(公告)日：2007-08-16
申请号：US11353529
申请日：2006-02-14
申请人： Taiyi Cheng , Mark Hahm
发明人： Taiyi Cheng , Mark Hahm
IPC分类号： G06T1/00
CPC分类号： G06T1/20
摘要： A method and system for programmable breakpoints in an integrated embedded image and video accelerator are described. Aspects of the system may include circuitry that enables generation of control signals for pipeline processing of video data within a single chip by at least selecting a target location of the video data and generating an interrupt at a time instant corresponding to the pipeline processing of the target location. The system may enable programmable breakpoints to be set and/or triggered based on policies determined in executable software. The ability to set programmable breakpoints may enable flexible utilization of system memory resources.
摘要翻译：描述了集成嵌入式图像和视频加速器中可编程断点的方法和系统。系统的方面可以包括电路，其能够通过至少选择视频数据的目标位置并在对应于目标的流水线处理的时刻产生中断来产生用于在单个芯片内的视频数据的流水线处理的控制信号位置。该系统可以基于在可执行软件中确定的策略来设置和/或触发可编程断点。设置可编程断点的能力可以灵活地利用系统内存资源。

8. 发明申请

US20110013851A1 METHOD AND SYSTEM FOR PIPELINED PROCESSING IN AN INTEGRATED EMBEDDED IMAGE AND VIDEO ACCELERATOR 有权
标题翻译：集成嵌入式图像和视频加速器中管道处理的方法与系统
公开(公告)号：US20110013851A1
公开(公告)日：2011-01-20
申请号：US12839591
申请日：2010-07-20
申请人： Taiyi Cheng , Mark Hahm , Li Fung Chang
发明人： Taiyi Cheng , Mark Hahm , Li Fung Chang
IPC分类号： G06K9/36
CPC分类号： H04N19/42
摘要： A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data. Aspects of the system may also include circuitry that enables transformation, within the single chip, of a block of said video data while simultaneously encoding, within said single chip, a previously transformed block of video data
摘要翻译：描述了集成嵌入式图像和视频加速器中流水线处理的方法和系统。在集成嵌入式图像和视频加速器中用于流水线处理的系统的方面可以包括能够对单个芯片内的视频数据进行流水线处理的电路，其中流水线处理还可以包括对视频数据块进行解码，同时对先前解码的视频数据块。系统的方面还可以包括能够在单个芯片内转换所述视频数据的块的电路，同时在所述单个芯片内同时对先前变换的视频数据块进行编码

9. 发明申请

US20070192393A1 Method and system for hardware and software shareable DCT/IDCT control interface 审中-公开
标题翻译：硬件和软件可共享的DCT / IDCT控制接口的方法和系统
公开(公告)号：US20070192393A1
公开(公告)日：2007-08-16
申请号：US11353367
申请日：2006-02-14
申请人： Taiyi Cheng , Mark Hahm , Li Chang
发明人： Taiyi Cheng , Mark Hahm , Li Chang
IPC分类号： G06F17/14
CPC分类号： G06F17/147 , H04N19/42 , H04N19/60
摘要： Certain aspects of a method and system for hardware and software shareable DCT/IDCT control interface are provided. A single DCT/IDCT interface may be utilized to provide hardware or software control of a DCT/IDCT module. During hardware control the DCT/IDCT module may be utilized for JPEG compression, for example. During software control a CPU may utilize the DCT/IDCT module for audio, software, and/or video applications, for example. The interface may enable selecting a quantization table for use by the DCT/IDCT module. The interface may also enable selecting encoding or decoding operations to be performed by the DCT/IDCT module. The interface may also enable toggling between a first and a second portion of a data buffer utilized by the DCT/IDCT module. Moreover, the interface may enable starting processing of a data block by the DCT/IDCT module and indicating when the DCT/IDCT module has completed processing the data block.
摘要翻译：提供了硬件和软件可共享的DCT / IDCT控制接口的方法和系统的某些方面。可以使用单个DCT / IDCT接口来提供DCT / IDCT模块的硬件或软件控制。在硬件控制期间，DCT / IDCT模块可以用于例如JPEG压缩。在软件控制期间，例如，CPU可以将DCT / IDCT模块用于音频，软件和/或视频应用。该接口可以使得能够选择用于DCT / IDCT模块的量化表。该接口还可以使得能够选择要由DCT / IDCT模块执行的编码或解码操作。接口还可以使得能够切换由DCT / IDCT模块使用的数据缓冲器的第一和第二部分。此外，该接口可以使DCT / IDCT模块能够开始处理数据块，并且指示DCT / IDCT模块何时完成数据块的处理。

10. 发明授权

US08238415B2 Method and system for programmable breakpoints in an integrated embedded image and video accelerator 有权
标题翻译：集成嵌入式图像和视频加速器中可编程断点的方法和系统
公开(公告)号：US08238415B2
公开(公告)日：2012-08-07
申请号：US11353529
申请日：2006-02-14
申请人： Taiyi Cheng , Mark Hahm
发明人： Taiyi Cheng , Mark Hahm
IPC分类号： H04B1/00 , G06T1/20
CPC分类号： G06T1/20
摘要： A method and system for programmable breakpoints in an integrated embedded image and video accelerator are described. Aspects of the system may include circuitry that enables generation of control signals for pipeline processing of video data within a single chip by at least selecting a target location of the video data and generating an interrupt at a time instant corresponding to the pipeline processing of the target location. The system may enable programmable breakpoints to be set and/or triggered based on policies determined in executable software. The ability to set programmable breakpoints may enable flexible utilization of system memory resources.
摘要翻译：描述了集成嵌入式图像和视频加速器中可编程断点的方法和系统。系统的方面可以包括电路，其能够通过至少选择视频数据的目标位置并在对应于目标的流水线处理的时刻产生中断来产生用于在单个芯片内的视频数据的流水线处理的控制信号位置。该系统可以基于在可执行软件中确定的策略来设置和/或触发可编程断点。设置可编程断点的能力可以灵活地利用系统内存资源。

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