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1. 发明授权

US08921171B2 Method for forming gate structure, method for forming semiconductor device, and semiconductor device 有权
标题翻译：用于形成栅极结构的方法，用于形成半导体器件的方法和半导体器件
公开(公告)号：US08921171B2
公开(公告)日：2014-12-30
申请号：US13699734
申请日：2012-07-24
申请人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
发明人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/8238 , H01L21/823842 , H01L21/823857 , H01L27/092
摘要： A method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on the substrate; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming a first work function adjustment layer on the oxygen scavenging element layer; etching the first work function adjustment layer above the nMOSFET area; forming a second work function adjustment layer on the surface of the substrate; metal layer depositing and annealing to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.
摘要翻译：一种用于形成栅极结构的方法，包括：提供衬底，其中所述衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且每个栅极沟槽设置在底部具有栅极电介质层; 在所述衬底上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成第一功函数调整层; 蚀刻nMOSFET区域上方的第一功函数调整层; 在所述基板的表面上形成第二功函数调整层; 金属层沉积和退火以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。

2. 发明申请

US20140015068A1 Gate Structure, Semiconductor Device and Methods for Forming the Same 审中-公开
标题翻译：门结构，半导体器件及其形成方法
公开(公告)号：US20140015068A1
公开(公告)日：2014-01-16
申请号：US13699731
申请日：2012-07-24
申请人： Hong Yang , Wenwu Wang , Huaxiang Yin , Jiang Yan , Xueli Ma
发明人： Hong Yang , Wenwu Wang , Huaxiang Yin , Jiang Yan , Xueli Ma
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L29/495 , H01L21/28008 , H01L21/28088 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： The disclosure relates to a gate structure, a semiconductor device and methods for forming the same. An embodiment of the disclosure provides a method for forming a gate structure, including: providing a substrate; forming an interface layer on the substrate; forming a gate dielectric layer on the interface layer; forming a gate dielectric capping layer on the gate dielectric layer; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming an oxygen scavenging element capping layer on the oxygen scavenging element layer; performing Post-Metallization Annealing; performing etching until the etching stop layer is exposed; forming a work function adjustment layer on the etching stop layer; and forming a gate layer on the work function adjustment layer.
摘要翻译：本公开涉及一种栅极结构，半导体器件及其形成方法。本公开的实施例提供了一种用于形成栅极结构的方法，包括：提供基板; 在衬底上形成界面层; 在界面层上形成栅介电层; 在所述栅极电介质层上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成氧清除元件盖层; 执行金属后退火; 进行蚀刻，直到蚀刻停止层露出为止; 在所述蚀刻停止层上形成功函数调整层; 以及在所述功函数调整层上形成栅极层。

3. 发明申请

US20140015063A1 Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device 有权
标题翻译：形成栅极结构的方法，形成半导体器件的方法和半导体器件
公开(公告)号：US20140015063A1
公开(公告)日：2014-01-16
申请号：US13699734
申请日：2012-07-24
申请人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
发明人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/8238 , H01L21/823842 , H01L21/823857 , H01L27/092
摘要： A method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on the substrate; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming a first work function adjustment layer on the oxygen scavenging element layer; etching the first work function adjustment layer above the nMOSFET area; forming a second work function adjustment layer on the surface of the substrate; metal layer depositing and annealing to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.
摘要翻译：一种用于形成栅极结构的方法，包括：提供衬底，其中所述衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且每个栅极沟槽设置在底部具有栅极电介质层; 在所述衬底上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成第一功函数调整层; 蚀刻nMOSFET区域上方的第一功函数调整层; 在所述基板的表面上形成第二功函数调整层; 金属层沉积和退火以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。

4. 发明申请

US20140015062A1 Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device 审中-公开
标题翻译：形成栅极结构的方法，形成半导体器件的方法和半导体器件
公开(公告)号：US20140015062A1
公开(公告)日：2014-01-16
申请号：US13699732
申请日：2012-07-24
申请人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
发明人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823857 , H01L21/823842 , H01L27/092
摘要： An embodiment of the present disclosure provides a method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on a surface of the substrate; forming an oxygen scavenging element layer on the gate dielectric capping layer; forming an etching stop layer on the oxygen scavenging element layer; forming a work function adjustment layer on the etching stop layer; performing metal layer deposition and annealing process to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.
摘要翻译：本公开的实施例提供了一种用于形成栅极结构的方法，包括：提供衬底，其中衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且栅极沟槽在底部设置有栅极电介质层; 在所述衬底的表面上形成栅介电覆盖层; 在所述栅介质顶盖层上形成氧清除元件层; 在除氧元件层上形成蚀刻停止层; 在所述蚀刻停止层上形成功函数调整层; 执行金属层沉积和退火工艺以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。

5. 发明授权

US08802578B2 Method for forming tin by PVD 有权
标题翻译：用PVD形成锡的方法
公开(公告)号：US08802578B2
公开(公告)日：2014-08-12
申请号：US13695191
申请日：2012-07-26
申请人： Zuozhen Fu , Huaxiang Yin , Jiang Yan
发明人： Zuozhen Fu , Huaxiang Yin , Jiang Yan
IPC分类号： H01L21/203 , H01L21/02 , C23C14/34 , C23C14/54 , C23C14/06 , C23C14/18
CPC分类号： H01L21/02186 , C23C14/0641 , C23C14/18 , C23C14/34 , C23C14/54 , H01L21/2855
摘要： A method for forming titanium nitride by PVD is disclosed, comprising: generating ions of a noble gas by glow discharge under a vacuum condition that a nitrogen gas and the noble gas are supplied; nitriding a surface of a wafer and a surface of a titanium target with the nitrogen gas; bombarding the surface of the titanium target with the ions of the noble gas after they are accelerated in an electric field so that titanium ions and titanium nitride are sputtered; and forming a titanium nitride layer by depositing titanium nitride on the surface of the wafer in a magnetic field, while titanium ions are injected into the surface of the wafer so that stress is introduced into the titanium nitride layer, wherein non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased by increasing kinetic energy of titanium ions which are injected into the surface of the wafer. In the method for forming titanium nitride by PVD according to the present disclosure, kinetic energy of titanium ions which are injected into the surface of the wafer is increased by controlling process parameters so that non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased.
摘要翻译：公开了一种通过PVD形成氮化钛的方法，包括：在供给氮气和惰性气体的真空条件下通过辉光放电产生惰性气体的离子; 用氮气氮化晶片的表面和钛靶的表面; 在惰性气体的离子在电场中加速之后，用钛离子轰击钛靶的表面，从而溅射钛离子和氮化钛; 以及通过在磁场表面上沉积氮化钛而形成氮化钛层，同时将钛离子注入到晶片的表面中，使得应力被引入到氮化钛层中，其中非晶化部分通过提高注入到晶片表面的钛离子的动能来增加氮化钛层和氮化钛层中的应力。在根据本公开的通过PVD形成氮化钛的方法中，通过控制工艺参数来增加注入晶片表面的钛离子的动能，使得氮化钛层的非结晶部分和应力在氮化钛层增加。

6. 发明申请

US20140027857A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140027857A1
公开(公告)日：2014-01-30
申请号：US13812498
申请日：2012-08-27
申请人： Huaxiang Yin , Jiang Yan , Dapeng Chen
发明人： Huaxiang Yin , Jiang Yan , Dapeng Chen
IPC分类号： H01L27/088 , H01L29/66
CPC分类号： H01L27/088 , H01L21/82345 , H01L21/823842 , H01L27/092 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66666 , H01L29/7848
摘要： The present invention discloses a semiconductor device, comprising a substrate, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate stack structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, characterized in that each of the first gate stack structures comprises a first gate insulating layer, a first blocking layer, a first work function regulating layer and a resistance regulating layer, and each of the second gate stack structures comprises a second gate insulating layer, a first blocking layer, a second work function regulating layer, a first work function regulating layer and a resistance regulating layer.
摘要翻译：本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在两侧的衬底中的多个源极和漏极区域每个栅极间隔结构，所述多个栅极堆叠结构包括多个第一栅极叠层结构和多个第二栅极堆叠结构，其特征在于，每个第一栅极堆叠结构包括第一栅极绝缘层，第一阻挡层，第一功函数调节层和电阻调节层，并且每个第二栅极堆叠结构包括第二栅极绝缘层，第一阻挡层，第二功函数调节层，第一功函数调节层和电阻调节层。

7. 发明申请

US20140017906A1 METHOD FOR FORMING TIN BY PVD 有权
标题翻译： PVD方法
公开(公告)号：US20140017906A1
公开(公告)日：2014-01-16
申请号：US13695191
申请日：2012-07-26
申请人： Zuozhen Fu , Huaxiang Yin , Jiang Yan
发明人： Zuozhen Fu , Huaxiang Yin , Jiang Yan
IPC分类号： H01L21/02
CPC分类号： H01L21/02186 , C23C14/0641 , C23C14/18 , C23C14/34 , C23C14/54 , H01L21/2855
摘要： A method for forming titanium nitride by PVD is disclosed, comprising: generating ions of a noble gas by glow discharge under a vacuum condition that a nitrogen gas and the noble gas are supplied; nitriding a surface of a wafer and a surface of a titanium target with the nitrogen gas; bombarding the surface of the titanium target with the ions of the noble gas after they are accelerated in an electric field so that titanium ions and titanium nitride are sputtered; and forming a titanium nitride layer by depositing titanium nitride on the surface of the wafer in a magnetic field, while titanium ions are injected into the surface of the wafer so that stress is introduced into the titanium nitride layer, wherein non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased by increasing kinetic energy of titanium ions which are injected into the surface of the wafer. In the method for forming titanium nitride by PVD according to the present disclosure, kinetic energy of titanium ions which are injected into the surface of the wafer is increased by controlling process parameters so that non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased.
摘要翻译：公开了一种通过PVD形成氮化钛的方法，包括：在供给氮气和惰性气体的真空条件下，通过辉光放电产生惰性气体的离子; 用氮气氮化晶片的表面和钛靶的表面; 在电场加速后，用惰性气体的离子轰击钛靶的表面，从而溅射钛离子和氮化钛; 以及通过在磁场中在晶片的表面上沉积氮化钛而形成氮化钛层，同时将钛离子注入晶片的表面，使得应力被引入到氮化钛层中，其中非晶化部分通过提高注入到晶片表面的钛离子的动能来增加氮化钛层和氮化钛层中的应力。在根据本公开的通过PVD形成氮化钛的方法中，通过控制工艺参数来增加注入晶片表面的钛离子的动能，使得氮化钛层的非结晶部分和应力在氮化钛层增加。

8. 发明授权

US08853024B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08853024B2
公开(公告)日：2014-10-07
申请号：US13812498
申请日：2012-08-27
申请人： Huaxiang Yin , Jiang Yan , Dapeng Chen
发明人： Huaxiang Yin , Jiang Yan , Dapeng Chen
IPC分类号： H01L21/8238
CPC分类号： H01L27/088 , H01L21/82345 , H01L21/823842 , H01L27/092 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66666 , H01L29/7848
摘要： The present invention discloses a method for manufacturing a semiconductor device comprising the steps of: forming a plurality of source and drain regions in a substrate; forming a plurality of gate spacer structures and an interlayer dielectric layer around the gate spacer structures on the substrate, wherein the gate spacer structures enclose a plurality of first gate trenches and a plurality of second gate trenches; sequentially depositing a first gate insulating layer and a second gate insulating layer, a first blocking layer and a second work function regulating layer in the first and second gate trenches; performing selective etching to remove the second work function regulating layer from the first gate trenches to expose the first blocking layer; depositing a first work function regulating layer on the first blocking layer in the first gate trenches and on the second work function regulating layer in the second gate trenches; and depositing a resistance regulating layer on the first work function regulating layer in the first gate trenches and on the first work function regulating layer in the second gate trench.
摘要翻译：本发明公开了一种制造半导体器件的方法，包括以下步骤：在衬底中形成多个源极和漏极区; 在所述衬底上的所述栅极隔离物结构周围形成多个栅极间隔物结构和层间电介质层，其中所述栅极间隔物结构包围多个第一栅极沟槽和多个第二栅极沟槽; 在第一和第二栅极沟槽中依次沉积第一栅极绝缘层和第二栅极绝缘层，第一阻挡层和第二功函数调节层; 执行选择性蚀刻以从第一栅极沟槽去除第二功函数调节层以暴露第一阻挡层; 在第一栅极沟槽中的第一阻挡层上和第二栅极沟槽中的第二功函数调节层上沉积第一功函数调节层; 以及在第一栅极沟槽中的第一功函数调节层和第二栅沟中的第一功函数调节层上沉积电阻调节层。

9. 发明授权

US09419095B2 Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process 有权
标题翻译：最后一个进程中的伪栅极的制造方法和栅极最后工艺中的虚拟栅极的制造方法
公开(公告)号：US09419095B2
公开(公告)日：2016-08-16
申请号：US14119864
申请日：2012-12-12
申请人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
发明人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
IPC分类号： H01L21/338 , H01L29/66 , H01L29/423 , H01L29/51 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28123 , H01L29/42364 , H01L29/513 , H01L29/518
摘要： A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.
摘要翻译：提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成光致抗蚀剂线，并修整所形成的光致抗蚀剂线，使得修整的光致抗蚀剂线的宽度小于或等于22nm; 并根据修整的光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层无定形硅。

10. 发明授权

US09070744B2 Shallow trench isolation structure, manufacturing method thereof and a device based on the structure 有权
标题翻译：浅沟槽隔离结构，其制造方法和基于该结构的器件
公开(公告)号：US09070744B2
公开(公告)日：2015-06-30
申请号：US13519573
申请日：2011-08-03
申请人： Jiang Yan
发明人： Jiang Yan
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76232
摘要： The present invention relates to a shallow trench isolation structure, manufacturing method thereof and a device based on the structure. The present invention provides a method for manufacturing a shallow trench isolation (STI) structure, characterized in comprising the following steps: providing a semiconductor substrate; forming an insulating medium on said semiconductor substrate; etching a part of the insulating medium by using a mask to expose the semiconductor substrate thereunder, the unetched insulating medium forming STI regions; and epitaxially growing a semiconductor layer on said semiconductor substrate between said STI regions as an active region. With the method provided by the present invention, the problem of filling a small-size trench is solved and the problem of STI step height is overcome.
摘要翻译：本发明涉及一种浅沟槽隔离结构，其制造方法和基于该结构的器件。本发明提供一种制造浅沟槽隔离（STI）结构的方法，其特征在于包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成绝缘介质; 通过使用掩模蚀刻绝缘介质的一部分以暴露其下的半导体衬底，形成STI区的未蚀刻绝缘介质; 并且在所述STI区域之间的所述半导体衬底上外延生长半导体层作为有源区。利用本发明提供的方法，解决了填充小尺寸沟槽的问题，克服了STI步长的问题。

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