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1. 发明授权

US06507895B1 Method and apparatus for access demarcation 失效
标题翻译：访问分界的方法和装置
公开(公告)号：US06507895B1
公开(公告)日：2003-01-14
申请号：US09539665
申请日：2000-03-30
申请人： Hong Wang , Ralph Kling , Jeff Baxter , Konrad Lai
发明人： Hong Wang , Ralph Kling , Jeff Baxter , Konrad Lai
IPC分类号： G06F1202
CPC分类号： G06F12/0862 , G06F2212/6022 , G06F2212/6028
摘要： An embodiment of the present invention provides for an apparatus for memory access demarcation. Data is accessed from a first cache, which comprises a first set of addresses and corresponding data at each of the addresses in the first set. A plurality of addresses is generated for a second set of addresses. The second set of addresses follows the first set of addresses. The second set of addresses are calculated based on a fixed stride, where the second set of addresses are associated with data from a first stream. A plurality of addresses is generated for a third set of addresses. The third set of addresses follows the first set of addresses. Each address in the third set of addresses is generated by tracing a link associated with another address in the third set of addresses. The third set of addresses is associated with data from a second stream.
摘要翻译：本发明的实施例提供了一种用于存储器访问分界的装置。数据从第一高速缓存访问，第一高速缓存包括第一组地址中的第一组地址和相应的数据。为第二组地址生成多个地址。第二组地址遵循第一组地址。基于固定步幅计算第二组地址，其中第二组地址与来自第一流的数据相关联。为第三组地址生成多个地址。第三组地址遵循第一组地址。通过跟踪与第三组地址中的另一地址相关联的链接来生成第三组地址中的每个地址。第三组地址与来自第二个流的数据相关联。

2. 发明授权

US07437542B2 Identifying and processing essential and non-essential code separately 失效
标题翻译：分别识别和处理基本和非基本代码
公开(公告)号：US07437542B2
公开(公告)日：2008-10-14
申请号：US11331874
申请日：2006-01-13
申请人： Hong Wang , Ralph Kling , Yong-Fong Lee , David A. Berson , Michael A. Kozuch , Konrad Lai
发明人： Hong Wang , Ralph Kling , Yong-Fong Lee , David A. Berson , Michael A. Kozuch , Konrad Lai
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F8/41 , G06F9/3879
摘要： A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.
摘要翻译：共轭处理器包括具有主管线的指令集架构（ISA）可见部分和具有h流管线的h流部分。在共轭处理器上执行的二进制程序包括在主流水线上执行的基本部分和在h流管线上执行的非必要部分。非必要部分包括用于向主管道提供提示的提示微积分。共轭处理器还包括将触发器映射到h流目标的共轭映射表。触发器可以是指令属性，数据属性，状态属性或事件属性。当满足触发时，目标指定的h流代码在h-flow流水线中执行。

3. 发明申请

US20060155967A1 Processing essential and non-essential code separately 失效
公开(公告)号：US20060155967A1
公开(公告)日：2006-07-13
申请号：US11331874
申请日：2006-01-13
申请人： Hong Wang , Ralph Kling , Yong-Fong Lee , David Berson , Michael Kozuch , Konrad Lai
发明人： Hong Wang , Ralph Kling , Yong-Fong Lee , David Berson , Michael Kozuch , Konrad Lai
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F8/41 , G06F9/3879
摘要： A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.

4. 发明授权

US07020766B1 Processing essential and non-essential code separately 失效
标题翻译：分别处理基本和非基本代码
公开(公告)号：US07020766B1
公开(公告)日：2006-03-28
申请号：US09580755
申请日：2000-05-30
申请人： Hong Wang , Ralph Kling , Yong-Fong Lee , David A. Berson , Michael A. Kozuch , Konrad Lai
发明人： Hong Wang , Ralph Kling , Yong-Fong Lee , David A. Berson , Michael A. Kozuch , Konrad Lai
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F8/41 , G06F9/3879
摘要： A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.
摘要翻译：共轭处理器包括具有主管线的指令集架构（ISA）可见部分和具有h流管线的h流部分。在共轭处理器上执行的二进制程序包括在主流水线上执行的基本部分和在h流管线上执行的非必要部分。非必要部分包括用于向主管道提供提示的提示微积分。共轭处理器还包括将触发器映射到h流目标的共轭映射表。触发器可以是指令属性，数据属性，状态属性或事件属性。当满足触发时，目标指定的h流代码在h-flow流水线中执行。

5. 发明授权

US07069545B2 Quantization and compression for computation reuse 失效
公开(公告)号：US07069545B2
公开(公告)日：2006-06-27
申请号：US09751930
申请日：2000-12-29
申请人： Hong Wang , Perry Wang , Ralph Kling , Neil A. Chazin , John Shen
发明人： Hong Wang , Perry Wang , Ralph Kling , Neil A. Chazin , John Shen
IPC分类号： G06F9/44
CPC分类号： G06F8/4441
摘要： Software reuse instances are found from an execution trace through a process of quantization, discovery, and synthesis. Quantization includes mapping n-dimensional vectors that correspond to instructions, live-in states, and live-out states to one dimensional symbols, and arranging the symbols into a text in program execution order. Discovery includes the identification of recurrent symbols and recurrent phrases of symbols within the text. Recurrent symbols and phrases correspond to reuse instances. Compression algorithms are applied to identify the recurrent symbols and phrases. Synthesis can include correlating the reuse instances with the binary program to identify the reuse regions within the software program. Synthesis can also include generating non-essential code and corresponding triggers for a conjugate processor.

6. 发明授权

US07516312B2 Presbyopic branch target prefetch method and apparatus 失效
标题翻译：远视分支目标预取方法和装置
公开(公告)号：US07516312B2
公开(公告)日：2009-04-07
申请号：US10817263
申请日：2004-04-02
申请人： Hong Wang , Ralph Kling , Edward T. Grochowski , Kalpana Ramakrishnan
发明人： Hong Wang , Ralph Kling , Edward T. Grochowski , Kalpana Ramakrishnan
IPC分类号： G06F15/00 , G06F9/00
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3848
摘要： An instruction prefetch apparatus includes a branch target buffer (BTB), a presbyopic target buffer (PTB) and a prefetch stream buffer (PSB). The BTB includes records that map branch addresses to branch target addresses, and the PTB includes records that map branch target addresses to subsequent branch target addresses. When a branch instruction is encountered, the BTB can predict the dynamically adjacent subsequent block entry location as the branch target address in the record that also includes the branch instruction address. The PTB can predict multiple subsequent blocks by mapping the branch target address to subsequent dynamic blocks. The PSB holds instructions prefetched from subsequent blocks predicted by the PTB.
摘要翻译：指令预取装置包括分支目标缓冲器（BTB），远视目标缓冲器（PTB）和预取流缓冲器（PSB）。 BTB包括将分支地址映射到分支目标地址的记录，PTB包括将分支目标地址映射到后续分支目标地址的记录。当遇到分支指令时，BTB可以将动态相邻的后续块条目位置预测为记录中还包括分支指令地址的分支目标地址。 PTB可以通过将分支目标地址映射到后续动态块来预测多个后续块。 PSB保存由PTB预测的后续块预取的指令。

7. 发明授权

US06848043B1 Optimal redundant arithmetic for microprocessors design 失效
标题翻译：微处理器设计的最优冗余算法
公开(公告)号：US06848043B1
公开(公告)日：2005-01-25
申请号：US09561261
申请日：2000-04-27
申请人： Thomas Y. Yeh , Hong Wang , Ralph Kling , Yong-Fong Lee
发明人： Thomas Y. Yeh , Hong Wang , Ralph Kling , Yong-Fong Lee
IPC分类号： G06F9/30 , G06F9/302 , G06F9/38
CPC分类号： G06F9/3826 , G06F9/30014 , G06F9/3808 , G06F9/3824 , G06F9/3836 , G06F9/3838
摘要： Methods and apparatus for improving system performance using redundant arithmetic are disclosed. In one embodiment, one or more dependency chains are formed. A dependency chain may comprise of two or more instructions. A first instruction may generate a result in a redundant form. A second instruction may accept the result from the first instruction as a first input operand. The instructions in the dependency chain may execute separately from instructions not in the dependency chain.
摘要翻译：公开了使用冗余算术来提高系统性能的方法和装置。在一个实施例中，形成一个或多个依赖链。依赖链可以由两个或更多个指令组成。第一条指令可以以冗余形式生成结果。第二指令可以将第一指令的结果接受为第一输入操作数。依赖关系链中的指令可以独立于不在依赖关系链中的指令执行。

8. 发明授权

US07051193B2 Register rotation prediction and precomputation 有权
公开(公告)号：US07051193B2
公开(公告)日：2006-05-23
申请号：US09819339
申请日：2001-03-28
申请人： Hong Wang , Christopher J. Hughes , Ralph Kling , Yong-Fong Lee , Daniel M. Lavery , John Shen , Jamison Collins
发明人： Hong Wang , Christopher J. Hughes , Ralph Kling , Yong-Fong Lee , Daniel M. Lavery , John Shen , Jamison Collins
IPC分类号： G06F9/38
CPC分类号： G06F9/325 , G06F9/30072 , G06F9/30101 , G06F9/384 , G06F9/3842
摘要： Instruction-level parallelism in software pipelined loops is exploited by predicting future register rotations. A processor includes an architected current frame marker register and at least one unarchitected frame marker register. Register rotation prediction is achieved by setting the register rotation of future iterations of a software loop to be a function of the unarchitected frame marker registers. True data dependencies remain, but the dependencies caused solely by register renaming are removed. Dynamic predication is used to predicate instructions from future iterations, allowing them to be squashed if dependencies are later found. The register renaming that results from the prediction can be included in instructions in a buffer, or a renaming stage in an execution pipeline can perform the renaming.

9. 发明授权

US06732260B1 Presbyopic branch target prefetch method and apparatus 有权
公开(公告)号：US06732260B1
公开(公告)日：2004-05-04
申请号：US09518939
申请日：2000-03-06
申请人： Hong Wang , Ralph Kling , Edward T. Grochowski , Kalpana Ramakrishnan
发明人： Hong Wang , Ralph Kling , Edward T. Grochowski , Kalpana Ramakrishnan
IPC分类号： G06F1500
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3848
摘要： An instruction prefetch apparatus includes a branch target buffer (BTB), a presbyopic target buffer (PTB) and a prefetch stream buffer (PSB). The BTB includes records that map branch addresses to branch target addresses, and the PTB includes records that map branch target addresses to subsequent branch target addresses. When a branch instruction is encountered, the BTB can predict the dynamically adjacent subsequent block entry location as the branch target address in the record that also includes the branch instruction address. The PTB can predict multiple subsequent blocks by mapping the branch target address to subsequent dynamic blocks. The PSB holds instructions prefetched from subsequent blocks predicted by the PTB.

10. 发明申请

US20070262885A1 Compact alphanumeric keyboard 有权
公开(公告)号：US20070262885A1
公开(公告)日：2007-11-15
申请号：US11879834
申请日：2007-07-18
申请人： Ralph Kling
发明人： Ralph Kling
IPC分类号： H03M11/00
CPC分类号： G06F3/0219 , G06F3/0202 , G06F3/0235 , H01H2217/036 , H01H2239/05
摘要： An apparatus comprises an input keypad having a plurality of keys. The input keypad outputs an output signal that is indicative of either a single depressed key or a plurality of depressed keys. The apparatus includes a processor for receiving the output signal by the input keypad and associating an alphabetic character with the output signal.

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