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1. 发明授权

US07228528B2 Building inter-block streams from a dynamic execution trace for a program 有权
标题翻译：从程序的动态执行跟踪构建块间流
公开(公告)号：US07228528B2
公开(公告)日：2007-06-05
申请号：US10609246
申请日：2003-06-26
申请人： Hong Wang , Marsha Eng , Perry Wang , John P. Shen , Gerolf F. Hoflehner , Daniel Lavery , Wei Li
发明人： Hong Wang , Marsha Eng , Perry Wang , John P. Shen , Gerolf F. Hoflehner , Daniel Lavery , Wei Li
IPC分类号： G06F9/45 , G06F15/00
CPC分类号： G06F8/447 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/3822 , G06F9/3853 , G06F9/3877
摘要： In one embodiment, the invention provides a method for the processing of instructions. A method which comprises analyzing a dynamic execution trace for a program; identifying at least one stream comprising a plurality of basic blocks in the dynamic execution trace; collecting metrics associated with the at least one stream; and optimizing the at least one stream based on the metrics.
摘要翻译：在一个实施例中，本发明提供了一种用于处理指令的方法。一种方法，包括分析程序的动态执行跟踪; 识别在所述动态执行跟踪中包括多个基本块的至少一个流; 收集与所述至少一个流相关联的度量; 以及基于所述度量来优化所述至少一个流。

2. 发明授权

US07260705B2 Apparatus to implement mesocode 有权
标题翻译：实现中间码的装置
公开(公告)号：US07260705B2
公开(公告)日：2007-08-21
申请号：US10608316
申请日：2003-06-26
申请人： Hong Wang , John Shen , Perry Wang , Marsha Eng , Gerolf F. Hoflehner , Dan Lavery , Wei Li , Alejandro Ramirez , Ed Grochowski
发明人： Hong Wang , John Shen , Perry Wang , Marsha Eng , Gerolf F. Hoflehner , Dan Lavery , Wei Li , Alejandro Ramirez , Ed Grochowski
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F8/447 , G06F9/30181 , G06F9/30196 , G06F9/3808 , G06F9/3822 , G06F9/3836 , G06F9/3844
摘要： In one embodiment, the invention provides a method for examining information about branch instructions. A method, comprising: examining information about branch instructions that reach a write-back stage of processing within a processor, defining a plurality of streams based on the examining, wherein each stream comprises a sequence of basic blocks in which only a last block in the sequence ends in a branch instruction, the execution of which causes program flow to branch, the remaining basic blocks in the stream each ending in a branch instruction, the execution of which does not cause program flow to branch.
摘要翻译：在一个实施例中，本发明提供了一种用于检查关于分支指令的信息的方法。一种方法，包括：检查关于在处理器内达到处理的回写阶段的分支指令的信息，基于所述检查来定义多个流，其中每个流包括一系列基本块，其中仅一序列在分支指令中结束，其执行导致程序流分支，流中的剩余基本块每个以分支指令结束，其执行不导致程序流分支。

3. 发明授权

US07603546B2 System, method and apparatus for dependency chain processing 有权
标题翻译：用于依赖关系链处理的系统，方法和装置
公开(公告)号：US07603546B2
公开(公告)日：2009-10-13
申请号：US10950693
申请日：2004-09-28
申请人： Satish Narayanasamy , Hong Wang , John Shen , Roni Rosner , Yoav Almog , Naftali Schwartz , Gerolf Hoflehner , Daniel LaVery , Wei Li , Xinmin Tian , Milind Girkar , Perry Wang
发明人： Satish Narayanasamy , Hong Wang , John Shen , Roni Rosner , Yoav Almog , Naftali Schwartz , Gerolf Hoflehner , Daniel LaVery , Wei Li , Xinmin Tian , Milind Girkar , Perry Wang
IPC分类号： G06F9/00 , G06F9/24 , G06F15/177
CPC分类号： G06F8/443 , G06F8/433 , G06F8/451
摘要： Embodiments of the present invention provide a method, apparatus and system which may include splitting a dependency chain into a set of reduced-width dependency chains; mapping one or more dependency chains onto one or more clustered dependency chain processors, wherein an issue-width of one or more of the clusters is adapted to accommodate a size of the dependency chains; and/or processing in parallel a plurality of dependency chains of a trace. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供了一种方法，装置和系统，其可以包括将依赖链分解成一组缩减宽度的依赖性链; 将一个或多个依赖关系链映射到一个或多个聚类依赖链处理器上，其中一个或多个所述簇的问题宽度适于适应所述依赖链的大小; 和/或并行处理多个跟踪的依赖性链。描述和要求保护其他实施例。

4. 发明申请

US20060070047A1 System, method and apparatus for dependency chain processing 有权
公开(公告)号：US20060070047A1
公开(公告)日：2006-03-30
申请号：US10950693
申请日：2004-09-28
申请人： Satish Narayanasamy , Hong Wang , John Shen , Roni Rosner , Yoav Almog , Naftali Schwartz , Gerolf Hoflehner , Daniel LaVery , Wei Li , Xinmin Tian , Milind Girkar , Perry Wang
发明人： Satish Narayanasamy , Hong Wang , John Shen , Roni Rosner , Yoav Almog , Naftali Schwartz , Gerolf Hoflehner , Daniel LaVery , Wei Li , Xinmin Tian , Milind Girkar , Perry Wang
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/433 , G06F8/451
摘要： Embodiments of the present invention provide a method, apparatus and system which may include splitting a dependency chain into a set of reduced-width dependency chains; mapping one or more dependency chains onto one or more clustered dependency chain processors, wherein an issue-width of one or more of the clusters is adapted to accommodate a size of the dependency chains; and/or processing in parallel a plurality of dependency chains of a trace. Other embodiments are described and claimed.

5. 发明申请

US20070079298A1 Thread-data affinity optimization using compiler 有权
标题翻译：线程数据亲和力优化使用编译器
公开(公告)号：US20070079298A1
公开(公告)日：2007-04-05
申请号：US11242489
申请日：2005-09-30
申请人： Xinmin Tian , Milind Girkar , David Sehr , Richard Grove , Wei Li , Hong Wang , Chris Newburn , Perry Wang , John Shen
发明人： Xinmin Tian , Milind Girkar , David Sehr , Richard Grove , Wei Li , Hong Wang , Chris Newburn , Perry Wang , John Shen
IPC分类号： G06F9/45
CPC分类号： G06F8/45
摘要： Thread-data affinity optimization can be performed by a compiler during the compiling of a computer program to be executed on a cache coherent non-uniform memory access (cc-NUMA) platform. In one embodiment, the present invention includes receiving a program to be compiled. The received program is then compiled in a first pass and executed. During execution, the compiler collects profiling data using a profiling tool. Then, in a second pass, the compiler performs thread-data affinity optimization on the program using the collected profiling data.
摘要翻译：线程数据亲和度优化可以在编译要在高速缓存相干非均匀内存访问（cc-NUMA）平台上执行的计算机程序时由编译器执行。在一个实施例中，本发明包括接收要编译的程序。接收的程序然后被编译成第一遍并被执行。在执行期间，编译器使用分析工具收集分析数据。然后，在第二遍，编译器使用收集的分析数据对程序执行线程数据关联优化。

6. 发明授权

US08037465B2 Thread-data affinity optimization using compiler 有权
标题翻译：线程数据亲和力优化使用编译器
公开(公告)号：US08037465B2
公开(公告)日：2011-10-11
申请号：US11242489
申请日：2005-09-30
申请人： Xinmin Tian , Milind Girkar , David C. Sehr , Richard Grove , Wei Li , Hong Wang , Chris Newburn , Perry Wang , John Shen
发明人： Xinmin Tian , Milind Girkar , David C. Sehr , Richard Grove , Wei Li , Hong Wang , Chris Newburn , Perry Wang , John Shen
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/45
摘要： Thread-data affinity optimization can be performed by a compiler during the compiling of a computer program to be executed on a cache coherent non-uniform memory access (cc-NUMA) platform. In one embodiment, the present invention includes receiving a program to be compiled. The received program is then compiled in a first pass and executed. During execution, the compiler collects profiling data using a profiling tool. Then, in a second pass, the compiler performs thread-data affinity optimization on the program using the collected profiling data.
摘要翻译：线程数据亲和度优化可以在编译要在高速缓存相干非均匀内存访问（cc-NUMA）平台上执行的计算机程序时由编译器执行。在一个实施例中，本发明包括接收要编译的程序。接收的程序然后被编译成第一遍并被执行。在执行期间，编译器使用分析工具收集分析数据。然后，在第二遍，编译器使用收集的分析数据对程序执行线程数据关联优化。

7. 发明申请

US20080163183A1 METHODS AND APPARATUS TO PROVIDE PARAMETERIZED OFFLOADING ON MULTIPROCESSOR ARCHITECTURES 审中-公开
标题翻译：在多处理器架构上提供参数化卸载的方法和装置
公开(公告)号：US20080163183A1
公开(公告)日：2008-07-03
申请号：US11618143
申请日：2006-12-29
申请人： Zhiyuan Li , Xinmin Tian , Wei Li , Hong Wang
发明人： Zhiyuan Li , Xinmin Tian , Wei Li , Hong Wang
IPC分类号： G06F9/45
CPC分类号： G06F8/456 , G06F2209/509
摘要： Methods and apparatus to provide parameterized offloading in multiprocessor systems are disclosed. An example method includes partitioning source code into a first task and a second task, and compiling object code from the source code, such that the first task is compiled to execute on a first processor core and the second task is compiled to execute on a second processor core, the assignment of the first task to the first core being dependent on an input parameter.
摘要翻译：公开了在多处理器系统中提供参数化卸载的方法和装置。示例性方法包括将源代码分割成第一任务和第二任务，以及从源代码编译目标代码，使得第一任务被编译为在第一处理器核上执行，并且第二任务被编译为在第二任务上执行处理器核心，将第一个任务分配给第一个内核取决于输入参数。

8. 发明申请

US20110307876A1 REGISTER MAPPING TECHNIQUES FOR EFFICIENT DYNAMIC BINARY TRANSLATION 有权
标题翻译：用于有效动态二进制翻译的注册映射技术
公开(公告)号：US20110307876A1
公开(公告)日：2011-12-15
申请号：US12815023
申请日：2010-06-14
申请人： Guilherme D. Ottoni , Hong Wang , Wei Li
发明人： Guilherme D. Ottoni , Hong Wang , Wei Li
IPC分类号： G06F9/45
CPC分类号： G06F8/441 , G06F9/45525
摘要： Generally, the present disclosure provides a system and method for mapping registers from a system with more registers to a system with fewer registers. Regions may be formed that include one or more blocks of code with relatively frequent register accesses. The most frequently accessed source registers may be mapped to target registers. Each block in the region may be bounded by a prologue and at least one epilogue. The prologue may be configured to implement register mapping and the epilogue(s) may be configured to manage program flow from a block in the region to another block in the region or to a block not in the region.
摘要翻译：通常，本公开提供了一种用于将具有更多寄存器的系统的寄存器映射到具有较少寄存器的系统的系统和方法。可以形成包括具有相对频繁的寄存器访问的一个或多个代码块的区域。最常访问的源寄存器可能被映射到目标寄存器。该区域中的每个块可以由前序和至少一个结尾界定。序言可以被配置为实现寄存器映射，并且结尾可以被配置为管理从该区域中的块到该区域中的另一块或者不在该区域中的块的程序流。

9. 发明授权

US09952864B2 System, apparatus, and method for supporting condition codes 有权
公开(公告)号：US09952864B2
公开(公告)日：2018-04-24
申请号：US12646762
申请日：2009-12-23
申请人： Guilherme D. Ottoni , Hong Wang , Christopher T. Weaver , Thomas A. Hartin , Wei Li , Jason W. Brandt
发明人： Guilherme D. Ottoni , Hong Wang , Christopher T. Weaver , Thomas A. Hartin , Wei Li , Jason W. Brandt
IPC分类号： G06F9/30
CPC分类号： G06F9/30058 , G06F9/30094 , G06F9/30116
摘要： An apparatus is described having decode circuitry to decode a first instruction, wherein the first instruction indicates that a copy of a plurality of condition codes bits is to be copied from a first register to a second register. The apparatus also has first execution circuitry to copy a plurality of condition code bits from a first register to a second register.

10. 发明授权

US08479176B2 Register mapping techniques for efficient dynamic binary translation 有权
标题翻译：用于高效动态二进制翻译的寄存器映射技术
公开(公告)号：US08479176B2
公开(公告)日：2013-07-02
申请号：US12815023
申请日：2010-06-14
申请人： Guilherme D. Ottoni , Hong Wang , Wei Li
发明人： Guilherme D. Ottoni , Hong Wang , Wei Li
IPC分类号： G06F9/45
CPC分类号： G06F8/441 , G06F9/45525
摘要： Generally, the present disclosure provides a system and method for mapping registers from a system with more registers to a system with fewer registers. Regions may be formed that include one or more blocks of code with relatively frequent register accesses. The most frequently accessed source registers may be mapped to target registers. Each block in the region may be bounded by a prologue and at least one epilogue. The prologue may be configured to implement register mapping and the epilogue(s) may be configured to manage program flow from a block in the region to another block in the region or to a block not in the region.
摘要翻译：通常，本公开提供了一种用于将具有更多寄存器的系统的寄存器映射到具有较少寄存器的系统的系统和方法。可以形成包括具有相对频繁的寄存器访问的一个或多个代码块的区域。最常访问的源寄存器可能被映射到目标寄存器。该区域中的每个块可以由前序和至少一个结尾界定。序言可以被配置为实现寄存器映射，并且结尾可以被配置为管理从该区域中的块到该区域中的另一块或者不在该区域中的块的程序流。

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