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1. 发明授权

US5378330A Method for polishing micro-sized structures 失效
标题翻译：抛光微型结构的方法
公开(公告)号：US5378330A
公开(公告)日：1995-01-03
申请号：US59466
申请日：1993-05-07
申请人： Hong Li , Stephen D. Senturia , David Volfson
发明人： Hong Li , Stephen D. Senturia , David Volfson
IPC分类号： C25F3/16 , C25F3/24
CPC分类号： C25F3/16 , C25F3/24
摘要： A method for polishing a substrate having at least one micro-sized structure. The method includes identifying a first region of the substrate on which a micro-sized structure is to be located. The first region is the region in which polishing is desired. A second region of the substrate, in which polishing is not desired, is also identified. An adhesion promoter is optionally applied to the substrate. The second region of the substrate is coated with a selected coating material that does not degrade substantially when exposed to a selected electrolyte. Material is removed from the first region, exposing a micro-sized structure. The coating material may be removed by the same machining process that forms the micro-sized structure. The substrate is submerged in the selected electrolyte so that the first region is exposed to the electrolyte. The first region of the substrate is electropolished. The coating is then optionally removed.
摘要翻译：一种用于抛光具有至少一个微尺寸结构的衬底的方法。该方法包括识别在其上定位有微尺寸结构的基底的第一区域。第一区域是需要抛光的区域。还鉴定了不需要抛光的衬底的第二区域。任选地将粘合促进剂施加到基底上。衬底的第二区域涂覆有当暴露于所选择的电解质时不会显着降解的选择的涂层材料。从第一区域去除材料，暴露微尺寸结构。可以通过形成微尺寸结构的相同的加工工艺去除涂层材料。将衬底浸没在所选择的电解质中，使得第一区域暴露于电解质。电解抛光底物的第一区域。然后可选地除去涂层。

2. 发明授权

US5106461A High-density, multi-level interconnects, flex circuits, and tape for tab 失效
标题翻译：高密度，多层互连，柔性电路和贴片胶带
公开(公告)号：US5106461A
公开(公告)日：1992-04-21
申请号：US632364
申请日：1990-12-21
申请人： David Volfson , Stephen D. Senturia
发明人： David Volfson , Stephen D. Senturia
IPC分类号： H01L23/538 , H05K3/00 , H05K3/06 , H05K3/10 , H05K3/20 , H05K3/38 , H05K3/42 , H05K3/46
CPC分类号： H05K3/4682 , H01L23/5383 , H01L23/5384 , H01L23/5387 , H05K3/423 , H01L2221/68345 , H01L2224/1147 , H01L2924/01019 , H01L2924/3011 , H05K2201/0154 , H05K2201/0355 , H05K2201/0394 , H05K2201/09563 , H05K2201/096 , H05K2203/016 , H05K2203/0733 , H05K2203/095 , H05K3/002 , H05K3/0023 , H05K3/0041 , H05K3/062 , H05K3/108 , H05K3/205 , H05K3/388 , H05K3/467 , Y10S438/977
摘要： A multi-layer interconnect structure of alternating dielectric (e.g., polyimide) and metal (e.g., copper) is built on a substrate supporting a continuous layer of metal. This metal layer is used as an electrode for plating vias through all the dielectric layers. Once the desired number of layers are formed, the substrate is removed and the continuous metal layer is patterned. Solid metal vias having nearly vertical side walls can be stacked vertically, producing good electrical and thermal transfer paths and permitting small, closely-spaced conductors. Further, by mixing geometrical shapes of conductors, a variety of useful structures can be achieved, such as controlled impedance transmission lines and multiconductor TAB tape with interconnects on tape of different dimensions than TAB fingers.
摘要翻译：在支撑连续金属层的基板上建立交替电介质（例如聚酰亚胺）和金属（例如铜）的多层互连结构。该金属层用作通过所有介电层电镀通孔的电极。一旦形成了期望数量的层，就去除衬底并且连续的金属层被图案化。具有几乎垂直侧壁的固体金属通孔可以垂直堆叠，产生良好的电和热传递路径并允许小的，紧密间隔的导体。此外，通过混合导体的几何形状，可以实现各种有用的结构，例如受控阻抗传输线和具有与TAB指不同的尺寸的带上的互连的多导体TAB带。

3. 发明授权

US4980034A High-density, multi-level interconnects, flex circuits, and tape for TAB 失效
标题翻译：高密度，多级互连，柔性电路和TAB的磁带
公开(公告)号：US4980034A
公开(公告)日：1990-12-25
申请号：US333179
申请日：1989-04-04
申请人： David Volfson , Stephen D. Senturia
发明人： David Volfson , Stephen D. Senturia
IPC分类号： H01L21/60 , H01L23/538 , H05K3/00 , H05K3/06 , H05K3/10 , H05K3/20 , H05K3/38 , H05K3/42 , H05K3/46
CPC分类号： H05K3/4682 , H01L23/5383 , H01L23/5384 , H01L23/5387 , H05K3/423 , H01L2221/68345 , H01L2224/1147 , H01L2924/01019 , H01L2924/3011 , H05K2201/0154 , H05K2201/0355 , H05K2201/0394 , H05K2201/096 , H05K2203/016 , H05K2203/0733 , H05K2203/095 , H05K3/002 , H05K3/0023 , H05K3/0041 , H05K3/062 , H05K3/108 , H05K3/205 , H05K3/388 , H05K3/467
摘要： A multi-layer interconnect structure of alternating dielectric (e.g., polyimide) and metal (e.g., copper) is built on a substrate supporting a continuous layer of metal. This metal layer is used as an electrode for plating vias through all the dielectric layers. Once the desired number of layers are formed, the substrate is removed and the continuous metal layer is patterned. Solid metal vias having nearly vertical side walls can be stacked vertically, producing good electrical and thermal transfer paths and permitting small, closely-spaced conductors. Further, by mixing geometrical shapes of conductors, a variety of useful structures can be achieved, such as controlled impedance transmission lines and multiconductor TAB tape with interconnects on tape of different dimensions than TAB fingers.
摘要翻译：在支撑连续金属层的基板上建立交替电介质（例如聚酰亚胺）和金属（例如铜）的多层互连结构。该金属层用作通过所有介电层电镀通孔的电极。一旦形成了期望数量的层，就去除衬底并且连续的金属层被图案化。具有几乎垂直侧壁的固体金属通孔可以垂直堆叠，产生良好的电和热传递路径并允许小的，紧密间隔的导体。此外，通过混合导体的几何形状，可以实现各种有用的结构，例如受控阻抗传输线和具有与TAB指不同的尺寸的带上的互连的多导体TAB带。

4. 发明申请

US20200319355A1 Rapid Prototyping of Single-Photon-Sensitive Silicon Avalanche Photodiodes 审中-公开
公开(公告)号：US20200319355A1
公开(公告)日：2020-10-08
申请号：US16778042
申请日：2020-01-31
申请人： Brian F. AULL , Joseph S. Ciampi , Renee D. Lambert , Christopher Leitz , Karl Alexander McIntosh , Steven Rabe , Kevin Ryu , Daniel R. SCHUETTE , David Volfson
发明人： Brian F. AULL , Joseph S. Ciampi , Renee D. Lambert , Christopher Leitz , Karl Alexander McIntosh , Steven Rabe , Kevin Ryu , Daniel R. SCHUETTE , David Volfson
IPC分类号： G01T1/24 , H01L27/146
摘要： A chip-to-chip integration process for rapid prototyping of silicon avalanche photodiode (APD) arrays has been developed. This process has several advantages over wafer-level 3D integration, including: (1) reduced cost per development cycle since a dedicated full-wafer read-out integrated circuit (ROIC) fabrication is not needed, (2) compatibility with ROICs made in previous fabrication runs, and (3) accelerated schedule. The process provides several advantages over previous processes for chip-to-chip integration, including: (1) shorter processing time as the chips can be diced, bump-bonded, and then thinned at the chip-level faster than in a wafer-level back-illumination process, and (2) the CMOS substrate provides mechanical support for the APD device, allowing integration of fast microlenses directly on the APD back surface. This approach yields APDs with low dark count rates (DCRs) and higher radiation tolerance for harsh environments and can be extended to large arrays of APDs.

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