专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110007594A1 MULTI-CHANNEL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF REFRESHING THE SAME 有权
标题翻译：多通道半导体存储器件及其刷新方法
公开(公告)号：US20110007594A1
公开(公告)日：2011-01-13
申请号：US12825935
申请日：2010-06-29
申请人： Ho-Young Kim , Woo-Pyo Jeong
发明人： Ho-Young Kim , Woo-Pyo Jeong
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40618
摘要： A multi-channel semiconductor memory device and a method of refreshing the same. In the multi-channel semiconductor memory device and method, a common refresh controller is prepared to detect refresh operation states of a plurality of sub-memory circuits (e.g. ICs) and to adjust refresh operation times of multiple sub-memory ICs so that two or more sub-memory ICs do not simultaneously perform a refresh operation, thereby reducing the peak current.
摘要翻译：一种多通道半导体存储器件及其刷新方法。在多通道半导体存储器件和方法中，准备公共刷新控制器以检测多个子存储器电路（例如IC）的刷新操作状态，并调整多个子存储器IC的刷新操作时间，使得两个或更多的子存储器IC不同时执行刷新操作，从而降低峰值电流。

2. 发明授权

US08675436B2 Multi-channel semiconductor memory device and method of refreshing the same 有权
标题翻译：多通道半导体存储器件及其刷新方法
公开(公告)号：US08675436B2
公开(公告)日：2014-03-18
申请号：US12825935
申请日：2010-06-29
申请人： Ho-Young Kim , Woo-Pyo Jeong
发明人： Ho-Young Kim , Woo-Pyo Jeong
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40618
摘要： A multi-channel semiconductor memory device and a method of refreshing the same. In the multi-channel semiconductor memory device and method, a common refresh controller is prepared to detect refresh operation states of a plurality of sub-memory circuits (e.g. ICs) and to adjust refresh operation times of multiple sub-memory ICs so that two or more sub-memory ICs do not simultaneously perform a refresh operation, thereby reducing the peak current.
摘要翻译：一种多通道半导体存储器件及其刷新方法。在多通道半导体存储器件和方法中，准备公共刷新控制器以检测多个子存储器电路（例如IC）的刷新操作状态，并调整多个子存储器IC的刷新操作时间，使得两个或更多的子存储器IC不同时执行刷新操作，从而降低峰值电流。

3. 发明申请

US20070014177A1 Apparatus and method for supplying power voltages in active and stand-by modes 有权
标题翻译：在主动和待机模式下提供电源电压的装置和方法
公开(公告)号：US20070014177A1
公开(公告)日：2007-01-18
申请号：US11481724
申请日：2006-07-06
申请人： Woo-Pyo Jeong
发明人： Woo-Pyo Jeong
IPC分类号： G11C5/14
CPC分类号： G11C5/143 , G11C11/417
摘要： A first voltage generator generates an active power voltage at a first power line having a decoupling capacitor coupled thereto. A second voltage generator generates a standby power voltage at a second power line. A switch is coupled between the first and second power lines. The switch is closed and the second voltage generator is disabled for an active mode of operation. The decoupling capacitor speeds up charging of the second power line to the active power voltage.
摘要翻译：第一电压发生器在具有耦合到其的去耦电容器的第一电力线上产生有功功率电压。第二电压发生器在第二电力线上产生备用电源电压。开关耦合在第一和第二电力线之间。开关闭合，第二个电压发生器被禁用为主动运行模式。去耦电容器将第二电源线的充电速度提高到有功功率电压。

4. 发明申请

US20090209061A1 METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE 有权
标题翻译：制造半导体封装的方法
公开(公告)号：US20090209061A1
公开(公告)日：2009-08-20
申请号：US12367596
申请日：2009-02-09
申请人： Woo-Pyo Jeong
发明人： Woo-Pyo Jeong
IPC分类号： H01L21/82
CPC分类号： H01L25/50 , H01L23/3128 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/91 , H01L25/0655 , H01L27/0207 , H01L27/105 , H01L2223/54406 , H01L2224/0401 , H01L2224/05553 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73257 , H01L2224/73265 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/078 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided is a semiconductor package and method of manufacturing same. The method includes: forming a plurality of semiconductor chips which have the same pattern direction on a semiconductor substrate, each of which includes a memory cell region, a peripheral region and a pad region, and in each of which the pad region is disposed in an edge region; separating the semiconductor chips, which are formed on the semiconductor substrate, from one another; and disposing semiconductor chips, which are selected from the separated semiconductor chips, on a package substrate by changing the pattern directions of the selected semiconductor chips and arranging pad regions of the selected semiconductor chips in a center region of the package substrate.
摘要翻译：提供一种半导体封装及其制造方法。该方法包括：在半导体衬底上形成具有相同图案方向的多个半导体芯片，每个半导体芯片包括存储单元区域，周边区域和焊盘区域，并且其中每个衬垫区域设置在边缘区域将形成在半导体衬底上的半导体芯片彼此分离; 并且通过改变所选择的半导体芯片的图案方向并将所选择的半导体芯片的焊盘区域布置在封装衬底的中心区域中，将从分离的半导体芯片中选择的半导体芯片设置在封装衬底上。

5. 发明授权

US08315118B2 Precharge method of semiconductor memory device and semiconductor memory device using the same 有权
标题翻译：半导体存储器件的预充电方法及使用其的半导体存储器件
公开(公告)号：US08315118B2
公开(公告)日：2012-11-20
申请号：US12767830
申请日：2010-04-27
申请人： Yong-Gyu Chu , Woo-Pyo Jeong
发明人： Yong-Gyu Chu , Woo-Pyo Jeong
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G11C7/12 , G11C11/4094
摘要： A precharge method of a semiconductor memory device that controls a precharge start time of each bank during a bank precharge operation, and a semiconductor memory device using the method, are provided. The device may latch an active or write order of respective banks and differently control precharge start times of the respective banks according to the latched active or write order during a plural-bank precharge operation to allow a plurality of banks to start precharge operations at different times.
摘要翻译：提供了一种半导体存储器件的预充电方法，其在银行预充电操作期间控制每个存储体的预充电开始时间，以及使用该方法的半导体存储器件。该装置可以锁存相应组的有效或写入顺序，并且在多组预充电操作期间根据锁存的有效或写入顺序不同地控制各个存储体的预充电开始时间，以允许多个存储体在不同时间开始预充电操作。

6. 发明授权

US08202764B2 Method of manufacturing semiconductor package 有权
标题翻译：制造半导体封装的方法
公开(公告)号：US08202764B2
公开(公告)日：2012-06-19
申请号：US12367596
申请日：2009-02-09
申请人： Woo-Pyo Jeong
发明人： Woo-Pyo Jeong
IPC分类号： H01L23/48
CPC分类号： H01L25/50 , H01L23/3128 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/91 , H01L25/0655 , H01L27/0207 , H01L27/105 , H01L2223/54406 , H01L2224/0401 , H01L2224/05553 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73257 , H01L2224/73265 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/078 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided is a semiconductor package and method of manufacturing same. The method includes: forming a plurality of semiconductor chips which have the same pattern direction on a semiconductor substrate, each of which includes a memory cell region, a peripheral region and a pad region, and in each of which the pad region is disposed in an edge region; separating the semiconductor chips, which are formed on the semiconductor substrate, from one another; and disposing semiconductor chips, which are selected from the separated semiconductor chips, on a package substrate by changing the pattern directions of the selected semiconductor chips and arranging pad regions of the selected semiconductor chips in a center region of the package substrate.
摘要翻译：提供一种半导体封装及其制造方法。该方法包括：在半导体衬底上形成具有相同图案方向的多个半导体芯片，每个半导体芯片包括存储单元区域，周边区域和焊盘区域，并且其中每个衬垫区域设置在边缘区域将形成在半导体衬底上的半导体芯片彼此分离; 并且通过改变所选择的半导体芯片的图案方向并将所选择的半导体芯片的焊盘区域布置在封装衬底的中心区域中，将从分离的半导体芯片中选择的半导体芯片设置在封装衬底上。

7. 发明授权

US07623408B2 Semiconductor memory device comprising data path controller and related method 有权
标题翻译：半导体存储器件包括数据路径控制器和相关方法
公开(公告)号：US07623408B2
公开(公告)日：2009-11-24
申请号：US11730653
申请日：2007-04-03
申请人： Woo-Pyo Jeong
发明人： Woo-Pyo Jeong
IPC分类号： G11C8/16
CPC分类号： G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/22 , G11C11/4076 , G11C11/4096
摘要： A semiconductor memory device and a related method are disclosed. The semiconductor memory device includes a data sensing output unit simultaneously providing first and second data to first and second data path lines, respectively; and a data output circuit, wherein the first and second data are serially output to an output terminal through the data output circuit. The device further includes a data transmitter operationally connecting the first data path line to the data output circuit and operationally connecting the second data path line to the data output circuit; and a data path controller connected between the data sensing output unit and the data transmitter, delaying the second data, and including first and second delay elements, wherein each of the first and second delay elements is disposed along one of the first and second data path lines.
摘要翻译：公开了一种半导体存储器件及相关方法。半导体存储器件包括数据感测输出单元，其分别向第一和第二数据路径线提供第一和第二数据; 和数据输出电路，其中第一和第二数据通过数据输出电路串行输出到输出端。该装置还包括数据发射机，可操作地将第一数据路径线连接到数据输出电路，并将第二数据路径线连接到数据输出电路; 连接在所述数据感测输出单元和所述数据发送器之间的数据路径控制器，延迟所述第二数据，并且包括第一和第二延迟元件，其中所述第一和第二延迟元件中的每一个沿着所述第一和第二数据路径线条。

8. 发明申请

US20110008932A1 METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：制造半导体封装的方法
公开(公告)号：US20110008932A1
公开(公告)日：2011-01-13
申请号：US12853745
申请日：2010-08-10
申请人： Woo-Pyo Jeong
发明人： Woo-Pyo Jeong
IPC分类号： H01L21/50
CPC分类号： H01L25/50 , H01L23/3128 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/91 , H01L25/0655 , H01L27/0207 , H01L27/105 , H01L2223/54406 , H01L2224/0401 , H01L2224/05553 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73257 , H01L2224/73265 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/078 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided is a semiconductor package and method of manufacturing same. The method includes: forming a plurality of semiconductor chips which have the same pattern direction on a semiconductor substrate, each of which includes a memory cell region, a peripheral region and a pad region, and in each of which the pad region is disposed in an edge region; separating the semiconductor chips, which are formed on the semiconductor substrate, from one another; and disposing semiconductor chips, which are selected from the separated semiconductor chips, on a package substrate by changing the pattern directions of the selected semiconductor chips and arranging pad regions of the selected semiconductor chips in a center region of the package substrate.
摘要翻译：提供一种半导体封装及其制造方法。该方法包括：在半导体衬底上形成具有相同图案方向的多个半导体芯片，每个半导体芯片包括存储单元区域，周边区域和焊盘区域，并且其中每个衬垫区域设置在边缘区域将形成在半导体衬底上的半导体芯片彼此分离; 并且通过改变所选择的半导体芯片的图案方向并将所选择的半导体芯片的焊盘区域布置在封装衬底的中心区域中，将从分离的半导体芯片中选择的半导体芯片设置在封装衬底上。

9. 发明授权

US07532538B2 Tri-state output driver arranging method and memory device using the same 有权
标题翻译：三态输出驱动器布置方法和使用其的存储器件
公开(公告)号：US07532538B2
公开(公告)日：2009-05-12
申请号：US11567664
申请日：2006-12-06
申请人： Seouk-Kyu Choi , Woo-Pyo Jeong
发明人： Seouk-Kyu Choi , Woo-Pyo Jeong
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1069
摘要： A memory device includes a first sensing amplifier to amplify data received from the memory array, a first driver to generate a first tri-state signal responsive to the amplified data from an first sense amplifier and to provide the first tri-state signal to a data bus line, a second sensing amplifier to amplify data received from the memory array, and a second driver to generate a second tri-state signal responsive to the amplified data from an second sense amplifier and to provide the second tri-state signal to the data bus line, where the first sensing amplifier and the first driver are located in different regions of the device, and the second sensing amplifier and the second driver are located in a common region of the device.
摘要翻译：存储器件包括：第一感测放大器，用于放大从存储器阵列接收的数据;第一驱动器，用于响应于来自第一读出放大器的放大数据产生第一三态信号，并将第一三态信号提供给数据总线线路，用于放大从存储器阵列接收的数据的第二感测放大器，以及响应于来自第二读出放大器的放大数据产生第二三态信号的第二驱动器，并向数据提供第二三态信号总线线路，其中第一感测放大器和第一驱动器位于设备的不同区域中，第二感测放大器和第二驱动器位于设备的公共区域中。

10. 发明申请

US20080049540A1 Semiconductor memory device comprising data path controller and related method 有权
标题翻译：半导体存储器件包括数据路径控制器和相关方法
公开(公告)号：US20080049540A1
公开(公告)日：2008-02-28
申请号：US11730653
申请日：2007-04-03
申请人： Woo-Pyo Jeong
发明人： Woo-Pyo Jeong
IPC分类号： G11C8/00
CPC分类号： G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/22 , G11C11/4076 , G11C11/4096
摘要： A semiconductor memory device and a related method are disclosed. The semiconductor memory device includes a data sensing output unit simultaneously providing first and second data to first and second data path lines, respectively; and a data output circuit, wherein the first and second data are serially output to an output terminal through the data output circuit. The device further includes a data transmitter operationally connecting the first data path line to the data output circuit and operationally connecting the second data path line to the data output circuit; and a data path controller connected between the data sensing output unit and the data transmitter, delaying the second data, and including first and second delay elements, wherein each of the first and second delay elements is disposed along one of the first and second data path lines.
摘要翻译：公开了一种半导体存储器件及相关方法。半导体存储器件包括数据感测输出单元，其分别向第一和第二数据路径线提供第一和第二数据; 和数据输出电路，其中第一和第二数据通过数据输出电路串行输出到输出端。该装置还包括数据发射机，可操作地将第一数据路径线连接到数据输出电路，并将第二数据路径线连接到数据输出电路; 连接在所述数据感测输出单元和所述数据发送器之间的数据路径控制器，延迟所述第二数据，并且包括第一和第二延迟元件，其中所述第一和第二延迟元件中的每一个沿着所述第一和第二数据路径线条。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式