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1. 发明申请

US20100246660A1 Pulse-Sync Demodulator 有权
标题翻译：脉冲同步解调器
公开(公告)号：US20100246660A1
公开(公告)日：2010-09-30
申请号：US12374737
申请日：2007-07-27
申请人： Michiaki Matsuo , Hideki Aoyagi , Hitoshi Asano , Kazuya Toki
发明人： Michiaki Matsuo , Hideki Aoyagi , Hitoshi Asano , Kazuya Toki
IPC分类号： H03K9/04
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/0812 , H04B1/717 , H04B1/7183 , H04L7/0037
摘要： A received pulse signal based on an on-off keying modulation scheme is alternately sampled by AD conversion sections operated by a clock signal whose frequency is one-half of a transmission rate. In the synchronization, amounts of delay in sampling timing adjustment sections are made different from each other, whereby phases of two different points in a symbol pulse are sampled. An amount of delay in a variable delay section is adjusted in accordance with a result of comparison of the sampled values, thereby achieving synchronization. At the time of demodulation, the amount of delay in the variable delay section is held, and the amounts of delay in the sampling timing adjustment sections are switched to the same value, and the symbol pulse is alternately sampled. The sampled values are subjected to threshold value determination, and the determination result is subjected to parallel-to-serial conversion, whereby a demodulation output is acquired.
摘要翻译：基于开关键控调制方式的接收脉冲信号由频率为传输速率的二分之一的时钟信号操作的AD转换部分交替采样。在同步中，采样定时调整部分中的延迟量彼此不同，从而对符号脉冲中两个不同点的相位进行采样。根据采样值的比较结果调整可变延迟部分的延迟量，从而实现同步。在解调时，保持可变延迟部分中的延迟量，并将采样定时调整部分中的延迟量切换到相同的值，并且对符号脉冲进行交替采样。对采样值进行阈值判定，对判定结果进行并行到串行转换，从而得到解调输出。

2. 发明申请

US20100020864A1 PULSE TRANSMITTING DEVICE, PULSE RECEIVING DEVICE, PULSE COMMUNICATION SYSTEM, AND PULSE COMMUNICATION METHOD 审中-公开
标题翻译：脉冲发射装置，脉冲接收装置，脉冲通信系统和脉冲通信方法
公开(公告)号：US20100020864A1
公开(公告)日：2010-01-28
申请号：US12374994
申请日：2007-07-12
申请人： Michiaki Matsuo , Hitoshi Asano , Hideki Aoyagi , Kazuaki Takahashi , Yew Soo Eng
发明人： Michiaki Matsuo , Hitoshi Asano , Hideki Aoyagi , Kazuaki Takahashi , Yew Soo Eng
IPC分类号： H03K7/04 , H04L27/06
CPC分类号： H04L25/4906 , H04B1/7172 , H04B1/719 , H04L25/4902
摘要： A pulse transmitting device is provided to avoid interference between pulses due to multipath influence even in a high speed pulse transmission that is typical of a UWB by making use of a relatively simple method and to improve receiving quality. In the device, a pulse adjusting unit (110) generates pulses in response to transmitting data, a non-use interval setting unit (120) sets up a non-use interval where the pulses generated by the pulse adjusting unit (110) are not transmitted on the basis of a delay time that a delayed pulse caused by the multipath delays from a main pulse and takes until arriving at a communication partner. A pulse position adjusting unit (130) adjusts a pulse position not to transmit the pulses during the non-use pulse interval. An RF transmitting unit (140) converts the pulse, the position of which is adjusted by the pulse position adjusting unit, to a wireless frequency band and transmits a pulse wireless signal after the conversion to the communication partner.
摘要翻译：提供脉冲发送装置，即使在UWB的典型的高速脉冲传输中，通过利用相对简单的方法并且提高接收质量，也可以避免由于多路径影响引起的脉冲之间的干扰。在该装置中，脉冲调整单元（110）响应于发送数据产生脉冲，不使用间隔设定单元（120）设定由脉冲调整单元（110）生成的脉冲不是的非使用间隔基于由主脉冲的多径延迟引起的延迟脉冲的延迟时间发送，并且直到到达通信伙伴。脉冲位置调整单元（130）调整在不使用脉冲间隔期间不发送脉冲的脉冲位置。 RF发送单元（140）将其位置由脉冲位置调整单元调整的脉冲转换为无线频带，并且在转换到通信对方之后发送脉冲无线信号。

3. 发明授权

US08130883B2 Pulse signal reception device, pulsed QPSK signal reception device, and pulse signal reception method 失效
标题翻译：脉冲信号接收装置，脉冲QPSK信号接收装置和脉冲信号接收方法
公开(公告)号：US08130883B2
公开(公告)日：2012-03-06
申请号：US12297567
申请日：2007-04-12
申请人： Hideki Aoyagi , Hitoshi Asano , Michiaki Matsuo
发明人： Hideki Aoyagi , Hitoshi Asano , Michiaki Matsuo
IPC分类号： H03K7/02
CPC分类号： H04L7/0338 , H04L25/49 , H04L27/22 , H04L27/2338
摘要： A pulse signal reception device of a comparatively simple configuration detects a signal sampled at an optimal clock timing for a pulse modulation signal having a signal width shorter than a symbol frequency. In this device, a time division unit (103) samples a data signal at a clock signal rise edge and outputs the sampled data signals to counters (104-1 to 104-3), respectively. The counters (104-1 to 104-3) count the number of High levels when the data signal becomes High level within a predetermined period, and a maximum value detection unit (105) outputs maximum data string information on a data string counted by a counter in which the maximum number of High levels has been detected among the counters (104-1 to 104-3) to a selection data judgment unit (106). The selection data judgment unit (106) judges which data string sampled at a particular timing is to be selected as a demodulation data string.
摘要翻译：具有相对简单的配置的脉冲信号接收装置检测在具有比符号频率短的信号宽度的脉冲调制信号的最佳时钟定时采样的信号。在该装置中，时分单元（103）以时钟信号上升沿对数据信号进行采样，并将采样数据信号分别输出到计数器（104-1至104-3）。计数器（104-1至104-3）在预定时段内数据信号变为高电平时对高电平数进行计数，最大值检测单元（105）输出关于由数据信号计数的数据串的最大数据串信息计数器，其中在计数器（104-1至104-3）中检测到最大数量的高电平到计数器到选择数据判断单元（106）。选择数据判断单元（106）判断在特定定时采样的哪个数据串将被选择作为解调数据串。

4. 发明申请

US20090080540A1 PULSE TRANSMITTER, PULSE RECEIVER, PULSE TRANSMITTING METHOD, AND PULSE DEMODULATING METHOD 失效
标题翻译：脉冲发射器，脉冲接收器，脉冲发射方法和脉冲解调方法
公开(公告)号：US20090080540A1
公开(公告)日：2009-03-26
申请号：US12297561
申请日：2007-04-19
申请人： Hitoshi Asano , Hideki Aoyagi , Michiaki Matsuo
发明人： Hitoshi Asano , Hideki Aoyagi , Michiaki Matsuo
IPC分类号： H04B14/04
CPC分类号： H04L25/4902 , H04L7/0008 , H04L25/4917
摘要： A pulse transmitter having a relatively simple structure and generating a pulse modulating signal even at a high transmission rate. In the pulse transmitter, a symbol pulse generating part (103) generates a symbol pulse of amplitude level β when data S1 is “0,” and that of amplitude level &ggr; when data S1 is “1” in the first pulse slot section, the data pulse generating part (104) generates a data pulse of amplitude level 0 when data S2 to Sn is “0,” and that of amplitude level α when data S2 to Sn is “1” in a later pulse slot section. The relationship of the amplitude levels keep the relation α
摘要翻译：具有相对简单结构的脉冲发射器，即使在高传输速率下也产生脉冲调制信号。在脉冲发送器中，当数据S1为“0”时，符号脉冲发生部（103）生成振幅电平β的符号脉冲，当数据S1在第一脉冲时隙部分为“1”时，产生幅度电平γ的符号脉冲，当数据S2至Sn为“0”时，数据脉冲产生部分（104）生成振幅电平为0的数据脉冲，当数据S2至Sn在稍后的脉冲时隙部分中时，产生振幅电平α的数据脉冲。振幅水平的关系保持关系α<β<＆ggr。加法器（105）将符号脉冲和数据脉冲相加，并将该和作为脉冲调制信号输出。

5. 发明申请

US20090252258A1 PULSE SIGNAL RECEPTION DEVICE, PULSED QPSK SIGNAL RECEPTION DEVICE, AND PULSE SIGNAL RECEPTION METHOD 失效
标题翻译：脉冲信号接收装置，脉冲QPSK信号接收装置和脉冲信号接收方法
公开(公告)号：US20090252258A1
公开(公告)日：2009-10-08
申请号：US12297567
申请日：2007-04-12
申请人： Hideki Aoyagi , Hitoshi Asano , Michiaki Matsuo
发明人： Hideki Aoyagi , Hitoshi Asano , Michiaki Matsuo
IPC分类号： H04L7/00 , H04L27/22
CPC分类号： H04L7/0338 , H04L25/49 , H04L27/22 , H04L27/2338
摘要： A pulse signal reception device of a comparatively simple configuration detects a signal sampled at an optimal clock timing for a pulse modulation signal having a signal width shorter than a symbol frequency. In this device, a time division unit (103) samples a data signal at a clock signal rise edge and outputs the sampled data signals to counters (104-1 to 104-3), respectively. The counters (104-1 to 104-3) count the number of High levels when the data signal becomes High level within a predetermined period, and a maximum value detection unit (105) outputs maximum data string information on a data string counted by a counter in which the maximum number of High levels has been detected among the counters (104-1 to 104-3) to a selection data judgment unit (106). The selection data judgment unit (106) judges which data string sampled at a particular timing is to be selected as a demodulation data string.
摘要翻译：具有相对简单的配置的脉冲信号接收装置检测在具有比符号频率短的信号宽度的脉冲调制信号的最佳时钟定时采样的信号。在该装置中，时分单元（103）以时钟信号上升沿对数据信号进行采样，并将采样数据信号分别输出到计数器（104-1至104-3）。计数器（104-1至104-3）在预定时段内数据信号变为高电平时对高电平数进行计数，最大值检测单元（105）输出关于由数据信号计数的数据串的最大数据串信息计数器，其中在计数器（104-1至104-3）中检测到最大数量的高电平到计数器到选择数据判断单元（106）。选择数据判断单元（106）判断在特定定时采样的哪个数据串将被选择作为解调数据串。

6. 发明授权

US08755468B2 Pulse-sync demodulator 有权
标题翻译：脉冲同步解调器
公开(公告)号：US08755468B2
公开(公告)日：2014-06-17
申请号：US12374737
申请日：2007-07-27
申请人： Michiaki Matsuo , Hideki Aoyagi , Hitoshi Asano , Kazuya Toki
发明人： Michiaki Matsuo , Hideki Aoyagi , Hitoshi Asano , Kazuya Toki
IPC分类号： H04L27/06
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/0812 , H04B1/717 , H04B1/7183 , H04L7/0037
摘要： A received pulse signal based on an on-off keying modulation scheme is alternately sampled by AD conversion sections operated by a clock signal whose frequency is one-half of a transmission rate. In the synchronization, amounts of delay in sampling timing adjustment sections are made different from each other, whereby phases of two different points in a symbol pulse are sampled. An amount of delay in a variable delay section is adjusted in accordance with a result of comparison of the sampled values, thereby achieving synchronization. At the time of demodulation, the amount of delay in the variable delay section is held, and the amounts of delay in the sampling timing adjustment sections are switched to the same value, and the symbol pulse is alternately sampled. The sampled values are subjected to threshold value determination, and the determination result is subjected to parallel-to-serial conversion, whereby a demodulation output is acquired.
摘要翻译：基于开关键控调制方式的接收脉冲信号由频率为传输速率的二分之一的时钟信号操作的AD转换部分交替采样。在同步中，采样定时调整部分中的延迟量彼此不同，从而对符号脉冲中两个不同点的相位进行采样。根据采样值的比较结果调整可变延迟部分的延迟量，从而实现同步。在解调时，保持可变延迟部分中的延迟量，并将采样定时调整部分中的延迟量切换到相同的值，并且对符号脉冲进行交替采样。对采样值进行阈值判定，对判定结果进行并行到串行转换，从而得到解调输出。

7. 发明授权

US08121201B2 Pulse transmitter, pulse receiver, pulse transmitting method, and pulse demodulating method 失效
标题翻译：脉冲发射机，脉冲接收机，脉冲发射方式和脉冲解调方法
公开(公告)号：US08121201B2
公开(公告)日：2012-02-21
申请号：US12297561
申请日：2007-04-19
申请人： Hitoshi Asano , Hideki Aoyagi , Michiaki Matsuo
发明人： Hitoshi Asano , Hideki Aoyagi , Michiaki Matsuo
IPC分类号： H04B14/04
CPC分类号： H04L25/4902 , H04L7/0008 , H04L25/4917
摘要： A pulse transmitter having a relatively simple structure and generating a pulse modulating signal even at a high transmission rate. In the pulse transmitter, a symbol pulse generating part (103) generates a symbol pulse of amplitude level β when data S1 is “0,” and that of amplitude level &ggr; when data S1 is “1” in the first pulse slot section, the data pulse generating part (104) generates a data pulse of amplitude level 0 when data S2 to Sn is “0,” and that of amplitude level α when data S2 to Sn is “1” in a later pulse slot section. The relationship of the amplitude levels keep the relation α
摘要翻译：一种具有相对简单结构并且即使在高传输速率也产生脉冲调制信号的脉冲发射机。在脉冲发送器中，符号脉冲生成部（103）生成振幅电平“bgr”的符号脉冲，当数据S1为“0”时，幅度电平为“g”; 当第一脉冲时隙部分的数据S1为“1”时，数据脉冲产生部分（104）当数据S2至Sn为“0”时产生振幅电平为0的数据脉冲，当数据S2至 Sn在稍后的脉冲槽部分中为“1”。振幅水平的关系保持关系α<＆bgr; <＆ggr。加法器（105）将符号脉冲和数据脉冲相加，并将该和作为脉冲调制信号输出。

8. 发明授权

US07898312B2 Variable delay apparatus 失效
标题翻译：可变延迟装置
公开(公告)号：US07898312B2
公开(公告)日：2011-03-01
申请号：US12376024
申请日：2007-08-07
申请人： Hideki Aoyagi , Hitoshi Asano , Kazuya Toki , Michiaki Matsuo , Suguru Fujita
发明人： Hideki Aoyagi , Hitoshi Asano , Kazuya Toki , Michiaki Matsuo , Suguru Fujita
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00058
摘要： It is an object of the invention to provide a variable delay apparatus in which, even immediately after the delay amount of the variable delay apparatus is changed, a signal of a timing that is different from a set delay amount is not output. The variable delay apparatus of the invention includes: a variable delay block 108 having N (N is a natural number) delay elements 101a to 101n, and N selectors 102a to 102n; a variable delay block 109 having N delay elements 103a to 103n, and N selectors 104a to 104n; and a selector 107. After selection signals 105a to 105n and 106a to 106n are changed, and after an output timing of a delay amount set by the variable delay blocks 108, 109 is attained, the signal to be output is switched by the selector 107, thereby avoiding a situation where, immediately after the delay amount is changed, a signal of a timing that is different from the set delay amount is output as an output signal.
摘要翻译：本发明的目的是提供一种可变延迟装置，其中即使在可变延迟装置的延迟量之后立即改变与设置的延迟量不同的定时信号也不被输出。本发明的可变延迟装置包括：具有N（N是自然数）延迟元件101a至101n的可变延迟块108和N个选择器102a至102n; 具有N个延迟元件103a〜103n的可变延迟块109和N个选择器104a〜104n; 在选择信号105a至105n和106a至106n改变之后，并且在达到由可变延迟块108,109设置的延迟量的输出定时之后，通过选择器107切换要输出的信号，从而避免了在延迟量变化之后立即输出与设定的延迟量不同的定时的信号作为输出信号的情况。

9. 发明申请

US20090315605A1 VARIABLE DELAY APPARATUS 失效
标题翻译：可变延迟装置
公开(公告)号：US20090315605A1
公开(公告)日：2009-12-24
申请号：US12376024
申请日：2007-08-07
申请人： Hideki Aoyagi , Hitoshi Asano , Kazuya Toki , Michiaki Matsuo , Suguru Fujita
发明人： Hideki Aoyagi , Hitoshi Asano , Kazuya Toki , Michiaki Matsuo , Suguru Fujita
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00058
摘要： It is an object of the invention to provide a variable delay apparatus in which, even immediately after the delay amount of the variable delay apparatus is changed, a signal of a timing that is different from a set delay amount is not output. The variable delay apparatus of the invention includes: a variable delay block 108 having N (N is a natural number) delay elements 101a to 101n, and N selectors 102a to 102n; a variable delay block 109 having N delay elements 103a to 103n, and N selectors 104a to 104n; and a selector 107. After selection signals 105a to 105n and 106a to 106n are changed, and after an output timing of a delay amount set by the variable delay blocks 108, 109 is attained, the signal to be output is switched by the selector 107, thereby avoiding a situation where, immediately after the delay amount is changed, a signal of a timing that is different from the set delay amount is output as an output signal.
摘要翻译：本发明的目的是提供一种可变延迟装置，其中即使在可变延迟装置的延迟量之后立即改变与设置的延迟量不同的定时信号也不被输出。本发明的可变延迟装置包括：具有N（N是自然数）延迟元件101a至101n的可变延迟块108和N个选择器102a至102n; 具有N个延迟元件103a〜103n的可变延迟块109和N个选择器104a〜104n; 在选择信号105a至105n和106a至106n改变之后，并且在达到由可变延迟块108,109设置的延迟量的输出定时之后，通过选择器107切换要输出的信号，从而避免了在延迟量变化之后立即输出与设定的延迟量不同的定时的信号作为输出信号的情况。

10. 发明授权

US08777830B2 Paper folding device for three-folding sheet of paper 有权
标题翻译：三折纸张折纸装置
公开(公告)号：US08777830B2
公开(公告)日：2014-07-15
申请号：US13157563
申请日：2011-06-10
申请人： Teruhiko Toyoizumi , Takashi Watanabe , Hiroaki Takatsu , Hitoshi Asano , Takafumi Tanaka
发明人： Teruhiko Toyoizumi , Takashi Watanabe , Hiroaki Takatsu , Hitoshi Asano , Takafumi Tanaka
IPC分类号： B31F1/00
CPC分类号： B65H45/18 , B65H2220/09 , B65H2301/4227 , B65H2511/13 , B65H2511/30 , B65H2511/414 , B65H2511/416 , B65H2513/50 , B65H2801/27 , B65H2220/01 , B65H2220/02
摘要： In a paper folding device, a first driving unit for forming a first folding line on the paper moves a first folding plate member to the paper fed to a first feeding position until load on the first folding plate member reaches a prescribed value or higher. A time period from the start of driving of the first folding unit by the first driving unit to the start of driving of a second folding unit by a second driving unit is determined based on characteristic of paper.
摘要翻译：在纸张折叠装置中，用于在纸上形成第一折叠线的第一驱动单元将第一折叠板构件移动到馈送到第一馈送位置的纸张，直到第一折叠板构件上的负载达到规定值以上。基于纸张的特性确定从第一驱动单元开始驱动第一折叠单元到通过第二驱动单元驱动第二折叠单元的时间段。

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