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1. 发明申请

US20190026179A1 COMPUTING SYSTEM AND ERROR HANDLING METHOD FOR COMPUTING SYSTEM 审中-公开
公开(公告)号：US20190026179A1
公开(公告)日：2019-01-24
申请号：US16067825
申请日：2016-03-14
申请人： HITACHI, LTD.
发明人： Akihiko ARAKI , Masakuni AGETSUMA , Sachie TAJIMA , Takanobu SUZUKI , Masanori TAKADA
IPC分类号： G06F11/07 , G06F11/14
摘要： A computing system that can maintain reliability required of a storage program while causing the storage program to operate on an operating system (OS) is provided. A processor of the computing system executes an OS controlling a hardware device and a storage program operating on the OS and using the hardware device via the OS. The OS identifies an error status of the hardware device when receiving a notification of an error that has occurred to the hardware device, and notifies the storage program that operates on the OS of the error status when the error status satisfies a predetermined condition. The storage program determines error handling on the hardware device on the basis of the error status, and requests the OS to perform the determined error handling. The OS performs the determined error handling on the hardware device.

2. 发明申请

US20150026395A1 STORAGE SYSTEM AND MANAGEMENT METHOD OF CONTROL INFORMATION THEREIN 审中-公开
标题翻译：存储系统及其控制信息管理方法
公开(公告)号：US20150026395A1
公开(公告)日：2015-01-22
申请号：US14507197
申请日：2014-10-06
申请人： Hitachi, Ltd.
发明人： Akihiko ARAKI , Yusuke Nonaka
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0871 , G06F12/0246 , G06F12/0873 , G06F12/121 , G06F2212/1021 , G06F2212/222 , G06F2212/262 , G06F2212/282 , G06F2212/466 , G06F2212/7208
摘要： An embodiment of this invention divides a cache memory of a storage system into a plurality of partitions and information in one or more of the partitions is composed of data different from user data and including control information. The storage system dynamically swaps data between an LU storing control information and a cache partition. Through this configuration, in a storage system having an upper limit in the capacity of the cache memory, a large amount of control information can be used while access performance to control information is kept.
摘要翻译：本发明的一个实施例将存储系统的高速缓冲存储器划分为多个分区，并且一个或多个分区中的信息由与用户数据不同的数据组成并且包括控制信息。存储系统在LU存储控制信息和高速缓存分区之间动态地交换数据。通过这种配置，在具有高速缓冲存储器的容量上限的存储系统中，可以使用大量的控制信息，同时保持对控制信息的访问性能。

3. 发明申请

US20190095382A1 COMPUTER SYSTEM, PROCESSING METHOD, AND DRIVER PROGRAM 审中-公开
公开(公告)号：US20190095382A1
公开(公告)日：2019-03-28
申请号：US16083059
申请日：2016-07-28
申请人： HITACHI, LTD.
发明人： Noboru MORISHITA , Masakuni AGETSUMA , Akihiko ARAKI , Tomoki SEKIYAMA
IPC分类号： G06F15/167 , G06F9/48 , H04L12/24 , H04L29/08
摘要： A computer system includes a plurality of servers connected to each other via a communication line, each server including a memory and a processor, an OS program and a storage program. The storage program is executed by the processor, and one of the plurality of servers acts as a request source server while one of the other servers acts as a request destination server. When the request source server reads data from the request destination server, the processor of the request source server executes the storage program to transmit a data read request to the request destination server. The processor of the request destination server then executes a storage memory driver incorporated in the OS program to read the requested data from an own memory and transmit the read data to the request source server. The request source server then executes the storage program to acquire the data.

4. 发明申请

US20180173721A1 STORAGE SYSTEM AND STORAGE CONTROL METHOD 审中-公开
公开(公告)号：US20180173721A1
公开(公告)日：2018-06-21
申请号：US15579893
申请日：2015-07-27
申请人： Hitachi, Ltd.
发明人： Akihiko ARAKI , Yusuke NONAKA , Noboru MORISHITA
IPC分类号： G06F17/30 , G06F3/06
摘要： This storage system comprises a block interface, a block control unit, a file control unit, and shared memory. The file control unit and block control unit are coupled via a first memory-through path structured to pass through a first area of the shared memory, and via a second memory-through path structured to pass through a second area of the shared memory. The block control unit has a protocol control unit and a virtual driver; exchanges control information for the file control unit with the file control unit via the first memory-through path; uses the virtual driver to convert an I/O request passed from the file control unit via the second memory-through path and processes the result with a protocol processing unit; and bypasses the virtual driver and uses the protocol processing unit to process a block I/O request transferred from the block interface via a physical path.

5. 发明申请

US20170277914A1 COMPUTER SYSTEM AND CONTROL METHOD THEREFOR 审中-公开
公开(公告)号：US20170277914A1
公开(公告)日：2017-09-28
申请号：US15506967
申请日：2014-11-12
申请人： Hitachi, Ltd.
发明人： Akihiko ARAKI , Yusuke NONAKA , Masanori TAKADA , Naoya OKADA
IPC分类号： G06F21/73 , G06F3/06
CPC分类号： G06F3/064 , G06F3/0634 , G06F3/0635 , G06F11/20 , G06F11/2007 , G06F11/2017
摘要： When mounting hardware which is coupled to another portion by a plurality of paths with different applications, despite the hardware being a single device, and a failure occurs in any of the paths, there is a risk that the failure may propagate to other components unless the other paths are also blocked. In order to solve the problem described above, in a storage apparatus to which a device coupled by a plurality of coupling paths with different applications can be mounted, the present invention determines a block range at the time of an occurrence of a failure to be a device and a plurality of coupling paths coupled to the device, manages the block range, and upon an occurrence of a failure, executes failure handling which involves blocking an appropriate block range determined in advance by referring to the information.

6. 发明申请

US20160103629A1 STORAGE SYSTEM HAVING A PLURALITY OF FLASH PACKAGES 审中-公开
公开(公告)号：US20160103629A1
公开(公告)日：2016-04-14
申请号：US14970761
申请日：2015-12-16
申请人： HITACHI, LTD.
发明人： Akira YAMAMOTO , Sadahiro SUGIMOTO , Akihiko ARAKI , Masayuki YAMAMOTO
IPC分类号： G06F3/06
CPC分类号： G06F3/0631 , G06F3/0604 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0647 , G06F3/0665 , G06F3/0688 , G06F3/0689 , G06F12/0246 , G06F2212/7204 , G06F2212/7208 , G11C16/349
摘要： A storage system 100, which has a plurality of flash packages 230, has a function for minimizing the imbalance of the number of deletions of each block inside the flash package 230 and a block-unit capacity virtualization function, and efficiently manifests lessening of the imbalance of the number of deletions and reduction in the data storage capacity for the entire storage system 100 by having functions for calculating the number of deletions and the data occupancy of each flash package 230, and for transferring data between the flash packages 230 on the basis of the values of these number of deletions and data occupancy.

7. 发明申请

US20130132656A1 STORAGE SUBSYSTEM AND ITS DATA PROCESSING METHOD 审中-公开
标题翻译：存储子系统及其数据处理方法
公开(公告)号：US20130132656A1
公开(公告)日：2013-05-23
申请号：US13743505
申请日：2013-01-17
申请人： HITACHI, LTD.
发明人： Yoshiki KANO , Masanori TAKADA , Akira YAMAMOTO , Akihiko ARAKI , Masayuki YAMAMOTO , Jun KITAHARA , Sadahiro SUGIMOTO
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0613 , G06F3/0616 , G06F3/0659 , G06F3/0685 , G06F3/0688
摘要： The amount of data to be stored in a semiconductor nonvolatile memory can be reduced and overhead associated with data processing can be reduced. When a microprocessor receives a write request from a host computer and data D1 to D3 exist in a cache slot, the microprocessor reads the LBA of each piece of the data, manages each piece of the data D1 to D3 using a bitmap table by associating them with their LBAs, generates a specific command CMD based on the LBAs of the data D1 to D3, adds the data D1 to D3 and addresses ADD1 to ADD3 indicating where the data D1 to D3 are to be stored, to the specific command CMD, and sends it to an FMPK. The FMPK stores each piece of update data in a specified block in the flash memory based on the specific command CMD.
摘要翻译：可以减少要存储在半导体非易失性存储器中的数据量，并且可以减少与数据处理相关的开销。当微处理器接收到来自主计算机的写请求并且数据D1至D3存在于高速缓存槽中时，微处理器读取每条数据的LBA，使用位图表来管理每条数据D1至D3，通过将它们相关联与其LBA一起生成基于数据D1至D3的LBA的特定命令CMD，将数据D1至D3和指示数据D1至D3将被存储在哪里的地址ADD1至ADD3添加到特定命令CMD，以及发送到FMPK。 FMPK基于特定命令CMD将每条更新数据存储在闪存中的指定块中。

8. 发明申请

US20180203733A1 COMPUTER AND CONTROL METHOD FOR COMPUTER 审中-公开
公开(公告)号：US20180203733A1
公开(公告)日：2018-07-19
申请号：US15743630
申请日：2015-10-02
申请人： HITACHI, LTD.
发明人： Sachie TAJIMA , Masakuni AGETSUMA , Takanobu SUZUKI , Akihiko ARAKI
IPC分类号： G06F9/50 , G06F13/28 , G06F12/06
CPC分类号： G06F9/5016 , G06F9/5027 , G06F12/0646 , G06F12/0813 , G06F13/10 , G06F13/28 , G06F2212/1048 , G06F2212/604 , G06F2212/6042 , G06F2213/2806
摘要： By assigning a physically continuous memory area to a virtual storage apparatus operated on an OS, the performance of the virtual storage apparatus is secured. A processor operates an OS, and the processor executes a plurality of processes on the OS. The plurality of processes includes a first virtual storage apparatus. The first virtual storage apparatus executes an I/O process, and includes a cache for storing data that is subjected to the I/O process. The processor assigns a resource in a computer to the plurality of processes, and the processor creates area information that indicates physical addresses assigned to the processes in a memory. On the basis of the area information, the processor selects a continuous area, which is a physically continuous area from the memory and assigns the continuous area to the cache.

9. 发明申请

US20160196184A1 STORAGE SYSTEM AND STORAGE SYSTEM FAILURE MANAGEMENT METHOD 有权
标题翻译：存储系统和存储系统故障管理方法
公开(公告)号：US20160196184A1
公开(公告)日：2016-07-07
申请号：US14360402
申请日：2013-07-22
申请人： Hitachi, Ltd.
发明人： Akihiko ARAKI , Yusuke NONAKA , Masanori TAKADA
IPC分类号： G06F11/14
CPC分类号： G06F11/1417 , G06F11/0712 , G06F11/0793 , G06F2201/805 , G06F2201/85
摘要： When a failure occurs, the present invention makes it possible to reboot after completing prescribed failure processing for respective control parts.A storage system 10 comprises a controller 100 and a logical volume 23. The controller 100 comprises a processor 140 and a memory 150 that is used by the processor, and uses the processor to realize a plurality of control parts 101, 102, and 103. A block OS 101, which is an example of a first control part, controls a block access request to a disk device 21 (logical volume 23). A file OS 103, which is an example of a second control part, is managed by a hypervisor 102. When a failure has occurred inside the controller, the controller reboots after confirming that prescribed failure processing has been completed for each OS 101, 102, and 103.
摘要翻译：当发生故障时，本发明使得可以在对各个控制部分完成规定的故障处理之后重启。存储系统10包括控制器100和逻辑卷23.控制器100包括由处理器使用的处理器140和存储器150，并且使用处理器来实现多个控制部件101,102和103。作为第一控制部分的示例的块OS 101控制对盘装置21（逻辑卷23）的块访问请求。作为第二控制部的示例的文件OS 103由管理程序102管理。当在控制器内部发生故障时，控制器在确认对于每个OS 101,102完成了规定的故障处理之后重新启动，和103。

10. 发明申请

US20150317093A1 STORAGE SYSTEM 有权
标题翻译：存储系统
公开(公告)号：US20150317093A1
公开(公告)日：2015-11-05
申请号：US14762039
申请日：2013-12-24
申请人： HITACHI, LTD.
发明人： Naoya OKADA , Yusuke NONAKA , Akihiko ARAKI , Shintaro KUDO , Makio MIZUNO
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F3/0619 , G06F3/0647 , G06F3/0659 , G06F3/0688 , G06F3/0689 , G06F12/0638 , G06F12/08 , G06F12/0868 , G06F12/0875 , G06F12/0893 , G06F2212/222 , G06F2212/2228 , Y02D10/13
摘要： A storage controller has a processor, a volatile first cache memory that is coupled to the processor and that temporarily stores data, a nonvolatile second cache memory that is coupled to a microprocessor and that temporarily stores data, and a battery that is configured to supply electrical power to at least the processor and the first cache memory when a power stoppage has occurred. The second cache memory includes a dirty data area for storing dirty data, which is data that is not stored in the storage device, and a remaining area other than the dirty data area. When a power stoppage has occurred, the processor stores as target data in the remaining area of the second cache memory either all or a part of the data stored in the first cache memory.
摘要翻译：存储控制器具有处理器，耦合到处理器并临时存储数据的易失性第一高速缓冲存储器，耦合到微处理器并临时存储数据的非易失性第二高速缓冲存储器，以及被配置为提供电气的电池当发生停电时，至少将处理器和第一高速缓存存储器供电。第二高速缓冲存储器包括用于存储不存储在存储装置中的数据的脏数据区域和除脏数据区域以外的剩余区域的脏数据区域。当发生停电时，处理器将存储在第一高速缓冲存储器中的全部或一部分数据作为目标数据存储在第二高速缓冲存储器的剩余区域中。

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