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1. 发明授权

US4937480A BICMOS buffer circuit 失效
标题翻译： BICMOS缓冲电路
公开(公告)号：US4937480A
公开(公告)日：1990-06-26
申请号：US373263
申请日：1989-06-27
申请人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma
发明人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma
IPC分类号： G11C7/12 , G11C8/06 , G11C8/10 , G11C11/418
CPC分类号： G11C8/10 , G11C11/418 , G11C7/12 , G11C8/06
摘要： A semiconductor integrated circuit includes an input buffer circuit, a decoder circuit and a plurality of memory cells. Each of the input buffer circuit and the decoder circuit consists of a combination of bipolar transistors and MOS transistors. In this combination various measures are taken to increase the operation speed and to reduce the electric power consumption. In an example thereof the data line load for the memory cells is constituted by Schottky barrier type diodes. In another example the load used for the respective emitter follower transistors is constituted by an MOS transistor operating as a variable resistance. In still another example, in a CMOS NOR ciruit of the decoder circuit the number of P channel MOS transistors are fewer than the number of N channel MOS transistors.

2. 发明授权

US4858191A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US4858191A
公开(公告)日：1989-08-15
申请号：US131644
申请日：1987-12-11
申请人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma
发明人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma
IPC分类号： G11C7/12 , G11C8/06 , G11C8/10 , G11C11/418
CPC分类号： G11C8/10 , G11C11/418 , G11C7/12 , G11C8/06
摘要： A semiconductor integrated circuit includes an input buffer circuit, a decoder circuit and a plurality of memory cells. Each of the input buffer circuit and the decoder circuit consists of a combination of bipolar transistors and MOS transistors. In this combination various measures are taken to increase the operation speed and to reduce the electric power consumption. In an example thereof the data line load for the memory cells is constituted by Schottky barrier type diodes. In another example the load used for the respective emitter follower transistors is constituted by an MOS transistor operating as a variable resistance.In still another example, in a CMOS NOR circuit of the decoder circuit the number of P channel MOS transistors are fewer than the number of N channel MOS transistors.
摘要翻译：半导体集成电路包括输入缓冲电路，解码器电路和多个存储单元。输入缓冲电路和解码电路各自由双极晶体管和MOS晶体管组成。在这种组合中，采取各种措施来提高操作速度并降低电力消耗。在其示例中，存储单元的数据线负载由肖特基势垒型二极管构成。在另一示例中，用于各个射极跟随器晶体管的负载由作为可变电阻工作的MOS晶体管构成。在另一示例中，在解码器电路的CMOS NOR电路中，P沟道MOS晶体管的数量少于N沟道MOS晶体管的数量。

3. 发明授权

US4942555A Bi-MOS semiconductor memory having high soft error immunity 失效
标题翻译：具有高软误差抗扰度的Bi-MOS半导体存储器
公开(公告)号：US4942555A
公开(公告)日：1990-07-17
申请号：US376865
申请日：1989-07-07
申请人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma , Kiyoo Itoh
发明人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma , Kiyoo Itoh
IPC分类号： G11C11/418 , G11C11/419
CPC分类号： G11C11/418 , G11C11/419
摘要： A semiconductor memory is provided having high reliability, and which particularly prevents data destruction by rays, and the like. In a semiconductor memory for detecting memory data from the conduction ratio between a transistor of a flip-flop type memory cell connected to selected word line and data line pairs and a load device of the data line, an arrangement is provided for setting the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of a data transfer MOS transistor of the memory cell. The signal read out from the memory cell is then applied through the data line to a differential amplifier using the base or gate of a junction type transistor as its input. Particularly to set the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of the data transfer MOS transistor of the memory cell, a device having high driving capability such as a bipolar transistor is used as the load of the data line. The word line voltage is changed over to two stages so that the data line voltage V.sub.D and the word line voltage V.sub.W satisfy the relation V.sub.W V.sub.D +V.sub.TH in a write cycle (where V.sub.TH is the threshold voltage of NMOS inside the memory cell).
摘要翻译：提供了具有高可靠性的半导体存储器，并且特别地防止了由于光线的数据破坏等。在用于根据连接到所选字线的触发器型存储单元的晶体管与数据线对之间的导通率以及数据线的负载装置的导通比来检测存储器数据的半导体存储器中，提供了用于设置字线电压低于数据线电压和存储单元的数据传输MOS晶体管的阈值电压之和的电压。从存储单元读出的信号然后通过数据线施加到使用结型晶体管的基极或栅极作为其输入的差分放大器。特别是为了将字线电压设定为低于数据线电压和存储单元的数据传输MOS晶体管的阈值电压之和的电压，使用诸如双极型晶体管的具有高驱动能力的器件作为负载的数据线。字线电压转换为两级，使得数据线电压VD和字线电压VW在读周期中满足关系VW VD + VTH（其中VTH 是存储单元内的NMOS的阈值电压）。

4. 发明授权

US4928265A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US4928265A
公开(公告)日：1990-05-22
申请号：US266148
申请日：1988-11-02
申请人： Hisayuki Higuchi , Noriyuki Homma , Makoto Suzuki , Suguru Tachibana
发明人： Hisayuki Higuchi , Noriyuki Homma , Makoto Suzuki , Suguru Tachibana
IPC分类号： G11C11/416
CPC分类号： G11C11/416
摘要： Considering the dispersion in the access time of semiconductor memories, at least a first and a second memory circuit are connected to the output of a sense amplifier. The output of the sense amplifier is an input to these two memory circuits alternatively at different timings. The data stored in these memory circuits are alternately transferred to a data output circuit. Even when the access time becomes long, the desired sense data can be successively read out from the output of the data output circuit at a short time interval determined by the clock cycle. When the access time becomes short and even when a second data is generated from the output of the sense amplifier at the timing of transferring a first data in the first memory circuit to the data output circuit, the first data held in the first memory circuit is prevented from being renewed by the second data. In this case too, the desired sense data can be successively read out from the output of the data output circuit at a time interval determined by the clock cycle.
摘要翻译：考虑到半导体存储器的访问时间的偏差，至少第一和第二存储器电路连接到读出放大器的输出。读出放大器的输出是以不同的定时交替地输入到这两个存储器电路。存储在这些存储器电路中的数据被交替地传送到数据输出电路。即使当访问时间变长时，可以在由时钟周期确定的短时间间隔内从数据输出电路的输出端连续地读出期望的感测数据。当访问时间变短时，即使在将第一存储器电路中的第一数据传送到数据输出电路的定时从读出放大器的输出产生第二数据时，保持在第一存储器电路中的第一数据为防止第二个数据被更新。在这种情况下，也可以在由时钟周期确定的时间间隔内从数据输出电路的输出端连续读出期望的检测数据。

5. 发明授权

US4866673A BI-MOS semiconductor memory having high soft error immunity 失效
标题翻译：具有高软错误抗扰度的BI-MOS半导体存储器
公开(公告)号：US4866673A
公开(公告)日：1989-09-12
申请号：US38940
申请日：1987-04-16
申请人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma , Kiyoo Itoh
发明人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma , Kiyoo Itoh
IPC分类号： G11C11/41 , G11C11/416 , G11C11/418 , G11C11/419
CPC分类号： G11C11/418 , G11C11/419
摘要： A semiconductor memory is provided having high reliability, and which particularly prevents data destruction by .alpha. rays, and the like. In a semiconductor memory for detecting memory data from the conduction ratio between a transistor of a flip-flop type memory cell connected to selected word line and data line pairs and a load device of the data line, an arrangement is provided for setting the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of a data transfer MOS transistor of the memory cell. The signal read out from the memory cell is then applied through the data line to a differential amplifier using the base or gate of a junction type transistor as its input. Particularly to set the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of the data transfer MOS transistor of the memory cell, a device having high driving capability such as a bipolar transistor is used as the load of the data line. The word line voltage is changed over to two stages so that the data line voltage V.sub.D and the word line voltage V.sub.W satisfy the relation V.sub.W V.sub.D +V.sub.TH in a write cycle (where V.sub.TH is the threshold voltage of NMOS inside the memory cell).
摘要翻译：提供具有高可靠性的半导体存储器，并且特别地防止由α射线引起的数据破坏等。在用于根据连接到所选字线的触发器型存储单元的晶体管与数据线对之间的导通率以及数据线的负载装置的导通比来检测存储器数据的半导体存储器中，提供了用于设置字线电压低于数据线电压和存储单元的数据传输MOS晶体管的阈值电压之和的电压。从存储单元读出的信号然后通过数据线施加到使用结型晶体管的基极或栅极作为其输入的差分放大器。特别是为了将字线电压设定为低于数据线电压和存储单元的数据传输MOS晶体管的阈值电压之和的电压，使用诸如双极型晶体管的具有高驱动能力的器件作为负载的数据线。字线电压转换为两级，使得数据线电压VD和字线电压VW在读周期中满足关系VW VD + VTH（其中VTH 是存储单元内的NMOS的阈值电压）。

6. 发明授权

US5218567A Match detection circuit for cache memory apparatus 失效
标题翻译：高速缓冲存储器装置的匹配检测电路
公开(公告)号：US5218567A
公开(公告)日：1993-06-08
申请号：US789003
申请日：1991-11-07
申请人： Makoto Suzuki , Suguru Tachibana , Hisayuki Higuchi
发明人： Makoto Suzuki , Suguru Tachibana , Hisayuki Higuchi
IPC分类号： G06F12/08 , G06F12/10 , G11C15/04
CPC分类号： G06F12/1054 , G06F12/0895 , G11C15/04
摘要： A cache memory apparatus made up of a memory cell array (300) and a match detection circuit is disclosed. The match detection circuit produces a detection signal related to whether a search data coincides with a data read out of the memory cell array (300). The match detection circuit applies complementary signals (d, d) of the data read from the memory cell array (300) to the bases of bipolar differential transistors (10, 11), the gates of a pair of field effect transistors (16, 17) are supplied with complementary signals (a, a) of the search data, and the bases of a pair of emitter-follower transistors (12, 13) are connected to the collectors of the bipolar differential transistors (10, 11), thereby producing a detection signal (HITO) from the jointly-connected emitters thereof.
摘要翻译：公开了一种由存储单元阵列（300）和匹配检测电路构成的高速缓存存储装置。匹配检测电路产生与搜索数据是否与从存储单元阵列（300）读出的数据一致的检测信号。匹配检测电路将从存储单元阵列（300）读取的数据的互补信号（d，＆amp; upbar＆d）施加到双极差分晶体管（10,11）的基极，一对场效应晶体管（16， 17）被提供有搜索数据的互补信号（a，＆amp; upbar＆a），并且一对射极跟随器晶体管（12,13）的基极连接到双极差分晶体管（10,11）的集电极，从而从其共同连接的发射器产生检测信号（＆amp; upbar＆amp; H）。

7. 发明授权

US5253197A Semiconductor associative memory device with current sensing 失效
标题翻译：具有电流检测的半导体联想存储器件
公开(公告)号：US5253197A
公开(公告)日：1993-10-12
申请号：US580464
申请日：1990-09-11
申请人： Makoto Suzuki , Suguru Tachibana , Hisayuki Higuchi , Katsuhiro Shimohigashi , Takehisa Hayashi , Makoto Hanawa , Tadahiko Nishimukai
发明人： Makoto Suzuki , Suguru Tachibana , Hisayuki Higuchi , Katsuhiro Shimohigashi , Takehisa Hayashi , Makoto Hanawa , Tadahiko Nishimukai
IPC分类号： G06F12/08 , G06F12/10 , G11C15/04
CPC分类号： G11C15/04 , G06F12/0895 , G06F12/1054 , Y02B60/1225
摘要： In a first embodiment of a CAM (Content Addressable Memory) or cache memory of the present invention disclosed herein, comparing information stored in a memory cell with comparison input information is accomplished in a comparison circuit without first converting a readout current from the memory cell into voltage information. In another embodiment, a matching detection between first stored information outputted from a first memory cell array and second stored information outputted from a second memory cell array is accomplished by an integrally formed sensing and matching detection circuit which is characterized as having both sensing and matching detection capabilities. That is, the sensing and matching detection circuit senses both stored information and thereafter detects matching based on a sensing result.
摘要翻译：在本文公开的本发明的CAM（内容可寻址存储器）或高速缓冲存储器的第一实施例中，将存储在存储单元中的比较信息与比较输入信息进行比较，在比较电路中完成，而无需将来自存储单元的读出电流转换成电压信息。在另一个实施例中，从第一存储单元阵列输出的第一存储信息与从第二存储单元阵列输出的第二存储信息之间的匹配检测由一体形成的感测和匹配检测电路来实现，其特征在于具有检测和匹配检测能力也就是说，感测和匹配检测电路感测存储的信息，并且此后基于感测结果检测匹配。

8. 发明授权

US5107141A BiCMOS logic circuit using 0.5 micron technology and having an operating potential difference of less than 4 volts 失效
标题翻译： BiCMOS逻辑电路采用0.5微米技术，工作电位差小于4伏特
公开(公告)号：US5107141A
公开(公告)日：1992-04-21
申请号：US604454
申请日：1990-10-29
申请人： Kazuo Yano , Mitsuru Hiraki , Hisayuki Higuchi , Suguru Tachibana , Makoto Suzuki , Katsuhiro Shimohigashi
发明人： Kazuo Yano , Mitsuru Hiraki , Hisayuki Higuchi , Suguru Tachibana , Makoto Suzuki , Katsuhiro Shimohigashi
IPC分类号： H03K19/00 , H03K19/013 , H03K19/0944
CPC分类号： H03K19/0013 , H03K19/0136 , H03K19/09448
摘要： An output circuit portion of a BiCMOS logic circuit adapted to operating on a low voltage has an npn transistor Q5 connected between the power source Vcc and an output N6, and has an npn transistor Q6 connected between the output N6 and ground potential GND. The base of the npn transistor Q5 is driven by the drain output of p-channel MOSFETs MP3, MP4, and the base of the npn transistor Q6 is driven by the drain output of p-channel MOSFET QP5. When the power source voltage Vcc drops, the voltage applied between the drain and the source of MOSFET MP5 becomes small by the effect of V.sub.BE of the transistor Q6, but the drain current of the MOSFET MP5 changes little. Therefore, the BiCMOS circuit operates at high speeds (see FIG. 1) even when the power source voltage drops.
摘要翻译：适用于低电压工作的BiCMOS逻辑电路的输出电路部分具有连接在电源Vcc和输出N6之间的npn晶体管Q5，并具有连接在输出N6和地电位GND之间的npn晶体管Q6。 npn晶体管Q5的基极由p沟道MOSFET MP3，MP4的漏极输出驱动，npn晶体管Q6的基极由p沟道MOSFET QP5的漏极输出驱动。当电源电压Vcc下降时，通过晶体管Q6的VBE的影响，施加在MOSFET MP5的漏极和源极之间的电压变小，但MOSFET MP5的漏极电流变化较小。因此，即使当电源电压下降时，BiCMOS电路也以高速工作（参见图1）。

9. 发明授权

US4825274A Bi-CMOS semiconductor device immune to latch-up 失效
标题翻译： Bi-CMOS半导体器件免于闭锁
公开(公告)号：US4825274A
公开(公告)日：1989-04-25
申请号：US929910
申请日：1986-11-13
申请人： Hisayuki Higuchi , Makoto Suzuki
发明人： Hisayuki Higuchi , Makoto Suzuki
IPC分类号： H01L21/8249 , H01L27/06 , H01L27/092 , H01L27/02
CPC分类号： H01L27/0623 , H01L27/0921
摘要： A circuit including a Bi-CMOS semiconductor device of a structure capable of preventing the latch-up phenomenon from occurring when operated as an inverter or the like. The semiconductor device includes a MOS FET and a bipolar transistor merged with each other and having a PNPN or NPNP structure in a region to which minority carriers can migrate through diffusion and in which a same potential is applied to at least a pair of P-type and N-type regions or a backward voltage is applied across PN junctions in operation. The semiconductor device comprises electrodes provided in both P-type and N-type regions, respectively, which form one of the PN junctions, wherein a backward voltage not lower than 0.5 V is applied across the electrodes upon operating the device.
摘要翻译：包括具有能够防止当作为逆变器等操作时发生闩锁现象的结构的Bi-CMOS半导体器件的电路。半导体器件包括MOS FET和双极晶体管，它们彼此并联并且在少数载流子可以通过扩散迁移的区域中具有PNPN或NPNP结构，并且其中相同的电势施加到至少一对P型并且在操作中的PN结上施加N型区域或反向电压。半导体器件包括分别设置在P型和N型区域中的电极，其形成PN结中的一个，其中在操作器件时，电极上施加不低于0.5V的反向电压。

10. 发明授权

US09176462B2 Image forming apparatus having a drawer unit with a paper-feeding conveying path therein 有权
标题翻译：图像形成装置具有其中具有送纸输送路径的抽屉单元
公开(公告)号：US09176462B2
公开(公告)日：2015-11-03
申请号：US14102747
申请日：2013-12-11
申请人： Yoshihide Ohta , Joh Ebara , Hiroshi Ishii , Junichi Kawase , Kohta Takenaka , Tetsuji Nishikawa , Kohta Hirakawa , Toshihiro Shimada , Yusuke Funayama , Tsuyoshi Endo , Yusuke Masu , Makoto Suzuki
发明人： Yoshihide Ohta , Joh Ebara , Hiroshi Ishii , Junichi Kawase , Kohta Takenaka , Tetsuji Nishikawa , Kohta Hirakawa , Toshihiro Shimada , Yusuke Funayama , Tsuyoshi Endo , Yusuke Masu , Makoto Suzuki
IPC分类号： G03G15/00 , G03G21/00 , G03G21/16
CPC分类号： G03G21/1623 , G03G15/6502 , G03G21/1638 , G03G21/1647 , G03G21/1695 , G03G2215/00544 , G03G2215/00713 , G03G2221/1675
摘要： An image forming apparatus having a drawer unit that includes therein a paper-feeding conveying path for conveying a recording medium conveyed from a paper feeding unit on which the recording media are stacked to an image forming unit and/or a discharge conveying path for conveying the recording medium on which an image has been formed to a discharging unit, and be drawn out from an apparatus main body; a lock unit that locks the drawer unit to the apparatus main body; a straddle detecting unit that detects whether the recording medium straddles a conveying path in the apparatus main body and a conveying path in the drawer unit; and a controller that controls the lock unit to lock the drawer unit to the apparatus main body when the straddle detecting unit detects the straddle.
摘要翻译：一种具有抽屉单元的图像形成装置，其中包括一个送纸传送路径，用于将从其上叠放有记录介质的供纸单元输送的记录介质传送到图像形成单元和/或排出传送路径，用于传送已经形成图像的记录介质到排出单元，并从设备主体被拉出; 锁定单元，其将抽屉单元锁定到设备主体; 跨越检测单元，其检测记录介质是否跨越所述设备主体中的传送路径和所述抽屉单元中的传送路径; 以及控制器，当所述跨骑式检测单元检测到所述跨骑时，所述控制器控制所述锁定单元将所述抽屉单元锁定到所述装置主体。

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