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1. 发明授权

US5555527A Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook 失效
公开(公告)号：US5555527A
公开(公告)日：1996-09-10
申请号：US358606
申请日：1994-12-14
申请人： Hisakazu Kotani , Hironori Akamatsu , Tsutomu Fujita
发明人： Hisakazu Kotani , Hironori Akamatsu , Tsutomu Fujita
IPC分类号： G09G5/39 , G11C11/406 , G11C13/00
CPC分类号： G09G5/39 , G11C11/406 , G09G2360/123 , G09G5/001
摘要： A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

2. 发明授权

US6023440A Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook 失效
标题翻译：半导体存储器，运动图像存储存储器，运动图像存储装置，运动图像显示装置，静态图像存储存储器和电子笔记本
公开(公告)号：US6023440A
公开(公告)日：2000-02-08
申请号：US320577
申请日：1999-05-27
申请人： Hisakazu Kotani , Hironori Akamatsu , Tsutomu Fujita
发明人： Hisakazu Kotani , Hironori Akamatsu , Tsutomu Fujita
IPC分类号： G09G5/39 , G11C11/406 , G11C13/00
CPC分类号： G09G5/39 , G11C11/406 , G09G2360/123 , G09G5/001
摘要： A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.
摘要翻译：分割成多个子存储器阵列的存储器阵列设置在芯片上，使得如果通过子存储器阵列选择电路选择了指定的子存储器阵列，则执行正常的读取/写入操作，基于由一组外部地址信号指示的地址对子存储器阵列。同时，安装在芯片上的用于自刷新的时钟发生器产生用于自刷新的字线基本时钟和用于刷新的字线基本时钟，从而选择子存储阵列中的字线，其中尚未选中。在随后选择进行刷新操作的子存储阵列的预定时间之前，输出刷新停止信号，以强制中止刷新操作，从而防止存储单元的充电不足。多个子存储器阵列中的每一个存储顺序的图像数据组，一帧或一个场上的数据。

3. 发明授权

US5805524A Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook 失效
公开(公告)号：US5805524A
公开(公告)日：1998-09-08
申请号：US593851
申请日：1996-01-30
申请人： Hisakazu Kotani , Hironori Akamatsu , Tsutomu Fujita
发明人： Hisakazu Kotani , Hironori Akamatsu , Tsutomu Fujita
IPC分类号： G09G5/39 , G11C11/406 , G11C13/00
CPC分类号： G09G5/39 , G11C11/406 , G09G2360/123 , G09G5/001
摘要： A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

4. 发明授权

US5949733A Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook 失效
公开(公告)号：US5949733A
公开(公告)日：1999-09-07
申请号：US3821
申请日：1998-01-07
申请人： Hisakazu Kotani , Hironori Akamatsu , Tsutomu Fujita
发明人： Hisakazu Kotani , Hironori Akamatsu , Tsutomu Fujita
IPC分类号： G09G5/39 , G11C11/406 , G11C13/00
CPC分类号： G09G5/39 , G11C11/406 , G09G2360/123 , G09G5/001
摘要： A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

5. 发明授权

US5764566A Static random access memory capable of reducing stendly power consumption and off-leakage current 失效
标题翻译：静态随机存取存储器能够降低待机功耗和漏电流
公开(公告)号：US5764566A
公开(公告)日：1998-06-09
申请号：US893682
申请日：1997-07-11
申请人： Hironori Akamatsu , Toru Iwata , Hisakazu Kotani
发明人： Hironori Akamatsu , Toru Iwata , Hisakazu Kotani
IPC分类号： G11C11/412 , G11C11/417 , G11C11/413
CPC分类号： G11C11/412 , G11C11/417
摘要： When a memory chip is in a standby mode, a ground power supply line of a flip-flop forming a memory cell is intermittently placed in the floating state. A switching NMOS transistor is connected between the ground power supply line and a power supply VSS. The gate of the NMOS transistor is controlled by an activation signal. When entering the floating state, the ground power supply line is charged due to an off-leakage current flowing in the transistor of the memory cell. As a result, the voltage of the ground power supply line is increased from the voltage of the power supply VSS. Accordingly, the off-leakage current of the memory cell is reduced, whereby the standby-time power consumption of the memory chip is decreased. When the voltage of the ground power supply line keeps going up, it becomes impossible to read data held in the memory cell in a short time, resulting in the data being lost. In order to prevent the loss of the data, the switching NMOS transistor is made to intermittently turn on.
摘要翻译：当存储器芯片处于待机模式时，形成存储单元的触发器的接地电源线被间歇地置于浮置状态。开关NMOS晶体管连接在接地电源线和电源VSS之间。 NMOS晶体管的栅极由激活信号控制。当进入浮动状态时，由于在存储单元的晶体管中流过的漏电流导致接地电源线被充电。结果，接地电源线的电压从电源VSS的电压增加。因此，存储单元的泄漏电流减小，从而存储芯片的待机时功耗降低。当接地电源线的电压持续上升时，不可能在短时间内读取保存在存储单元中的数据，导致数据丢失。为了防止数据丢失，使开关式NMOS晶体管间歇地导通。

6. 发明授权

US5508963A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5508963A
公开(公告)日：1996-04-16
申请号：US209120
申请日：1994-03-11
申请人： Akihiro Sawada , Hiroyuki Yamauchi , Hironori Akamatsu , Shunichi Iwanari , Masashi Agata , Hirohito Kikukawa , Hisakazu Kotani
发明人： Akihiro Sawada , Hiroyuki Yamauchi , Hironori Akamatsu , Shunichi Iwanari , Masashi Agata , Hirohito Kikukawa , Hisakazu Kotani
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/785 , G11C29/80 , G11C29/808 , G11C29/83 , G11C29/84 , G11C29/846
摘要： N-piece redundant address comparing circuits are individually composed of impedance converting circuits, so that information using redundancy is transmitted as an impedance value. Consequently, even though the N becomes larger as the capacity of a memory becomes larger, a signal line having large capacitance and the node of a redundant judging circuit are not charged or discharged. A high-speed operation can be realized without being affected by the capacitance of the signal line or by the capacitance of the node of the redundant judging circuit.
摘要翻译： N段冗余地址比较电路分别由阻抗转换电路组成，从而使用冗余的信息作为阻抗值传输。因此，即使当存储器的容量变大时N变大，具有大电容的信号线和冗余判断电路的节点也不被充电或放电。可以实现高速操作，而不受信号线的电容或冗余判断电路的节点的电容的影响。

7. 发明授权

US5699300A Divided wordline memory arrangement having overlapping activation of wordlines during continuous access cycle 失效
标题翻译：分割的字线存储器布置在连续访问周期期间具有字线重叠的激活
公开(公告)号：US5699300A
公开(公告)日：1997-12-16
申请号：US341947
申请日：1994-11-16
申请人： Hironori Akamatsu , Tsuyoshi Shiragasawa , Junko Matsushima , Hisakazu Kotani
发明人： Hironori Akamatsu , Tsuyoshi Shiragasawa , Junko Matsushima , Hisakazu Kotani
IPC分类号： G11C11/401 , G11C7/10 , G11C8/14 , G11C8/18 , G11C11/409 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1015 , G11C8/14 , G11C8/18
摘要： A semiconductor memory device comprising memory cells arranged in a matrix with plural pairs of bit lines to be column addressed and connected to sense amplifiers, and word lines to be row addressed and divided into divisional word lines. Output signals of sense amplifiers selected by the column addressing are transferred to respective data lines. The divisional word lines are time-sequentially activated corresponding to the row addressing with the activated states of any two sequential divisional word lines overlapped for a fractional time of the full activation time. The sense amplifiers are grouped into plural groups with respective common column addresses. Each group of sense amplifiers have their outputs to be applied to respective data lines connected to a serial/parallel converter.
摘要翻译：一种半导体存储器件，包括以矩阵形式布置的存储器单元，其中多对位线被列地址并连接到读出放大器，并且字线被行寻址并分成划分字线。由列寻址选择的读出放大器的输出信号被传送到相应的数据线。分割字线对应于行寻址而被时间顺序地激活，其中任何两个连续分割字线的激活状态在完全激活时间的分数时间内重叠。感测放大器被分组成具有相应公共列地址的多个组。每组读出放大器的输出都被施加到连接到串行/并行转换器的相应数据线上。

8. 发明授权

US5999022A Signal transmission driver circuit, receiver circuit, and method thereof for transmitting and receiving information based on multiple periods and/or a delay function 失效
标题翻译：用于基于多个周期和/或延迟功能发送和接收信息的信号传输驱动电路，接收机电路及其方法
公开(公告)号：US5999022A
公开(公告)日：1999-12-07
申请号：US631914
申请日：1996-04-15
申请人： Toru Iwata , Hironori Akamatsu , Hisakazu Kotani , Hiroyuki Yamauchi , Akira Matsuzawa , Shoichiro Tada
发明人： Toru Iwata , Hironori Akamatsu , Hisakazu Kotani , Hiroyuki Yamauchi , Akira Matsuzawa , Shoichiro Tada
IPC分类号： H03K19/00 , H03K19/0185 , H03K3/00
CPC分类号： H03K19/01855 , H03K19/0016
摘要： A driver circuit which drives a signal line includes a first output section for outputting a reference voltage potential to the signal line during a first period and a second output section for outputting one of a first information voltage potential and a second information voltage potential in accordance with an input signal during a second period.
摘要翻译：驱动信号线的驱动器电路包括：第一输出部，用于在第一时段期间向信号线输出参考电压电位;以及第二输出部，用于输出第一信息电压电位和第二信息电压电位之一在第二时段期间的输入信号。

9. 发明授权

US5818782A Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory 失效
公开(公告)号：US5818782A
公开(公告)日：1998-10-06
申请号：US814507
申请日：1997-03-10
申请人： Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
发明人： Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , G11C13/00
CPC分类号： G11C7/1057 , G11C11/4096 , G11C5/025 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

10. 发明授权

US5293339A Semiconductor integrated circuit containing redundant memory element 失效
标题翻译：包含冗余存储元件的半导体集成电路
公开(公告)号：US5293339A
公开(公告)日：1994-03-08
申请号：US863268
申请日：1992-04-03
申请人： Toshikazu Suzuki , Hisakazu Kotani , Hironori Akamatsu
发明人： Toshikazu Suzuki , Hisakazu Kotani , Hironori Akamatsu
IPC分类号： G11C29/00 , G11C29/04 , G11C8/00 , H03K19/003
CPC分类号： G11C29/806 , G11C29/83 , G11C29/84
摘要： A semiconductor integrated circuit contains a plurality of programmable circuits each including a plurality of fuses and a first transistor which has a gate subjected to an address decoded signal, a drain connected to first ends of the fuses, and a source connected to a common precharge node. The address decoded signal results from decoding a first portion of an address signal for access to memory cells. The sources of the first transistors in the respective programmable circuits are connected to the common precharge node. A plurality of second transistors have gates subjected to a second portion of the address signal, sources connected to a first power supply line, and drains connected to second ends of the fuses in each of the programmable circuits respectively. The second portion of the address signal differs from the first portion of the address signal. A third transistor has a gate subjected to a precharge control signal, a source connected to a second power supply line, and a drain connected to the common precharge node.
摘要翻译：半导体集成电路包含多个可编程电路，每个可编程电路包括多个保险丝，第一晶体管具有经过地址解码信号的栅极，连接到保险丝的第一端的漏极和连接到公共预充电节点。地址解码信号是对解码访问存储单元的地址信号的第一部分而产生的。各个可编程电路中的第一晶体管的源极连接到公共预充电节点。多个第二晶体管具有经过地址信号的第二部分的栅极，分别连接到第一电源线的源和连接到每个可编程电路中的熔丝的第二端的漏极。地址信号的第二部分与地址信号的第一部分不同。第三晶体管具有经受预充电控制信号的栅极，连接到第二电源线的源极和连接到公共预充电节点的漏极。

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