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1. 发明授权

US4851934A Analog signal synthesizing processing circuit with periodic noise compensation 失效
标题翻译：具有周期噪声补偿的模拟信号合成处理电路
公开(公告)号：US4851934A
公开(公告)日：1989-07-25
申请号：US95953
申请日：1987-09-14
申请人： Hisaharu Takeuchi , Teruo Itami
发明人： Hisaharu Takeuchi , Teruo Itami
IPC分类号： H04N5/213 , G11B20/24 , H04N5/93 , H04N9/802
CPC分类号： H04N9/802 , G11B20/24
摘要： An analog signal synthesizing processing circuit with a periodic noise compensation generates analog signal of a plurality of audio signals and so forth containing noise generated almost periodically, for example by head switching of VTR, and plurality of analog signals containing the noise are phase-synchronized with given sampling clock signal and phase synchronizing circuit by timing oscillating circuit, the phase-synchronized signal is output from reproductive audio signal processing circuit, converted into digital signal by analog-digital converter and the noise contained in this converted signal is approximated from its preceding and following signal by compensation processing circuit and this approximated signal is converted into analog signal by digital-analog converter.
摘要翻译：具有周期性噪声补偿的模拟信号合成处理电路产生包含几乎周期性地产生的噪声的多个音频信号等的模拟信号，例如通过VTR的头切换，并且包含噪声的多个模拟信号与给定采样时钟信号和相位同步电路通过定时振荡电路，相位同步信号由生殖音频信号处理电路输出，由模拟数字转换器转换为数字信号，该转换信号中包含的噪声从前面和后面近似，通过补偿处理电路跟随信号，该近似信号由数模转换器转换为模拟信号。

2. 发明授权

US4796123A Slow reproducing apparatus for VTR or VCR using image memory 失效
标题翻译：使用图像存储器的VTR或VCR的慢速再现装置
公开(公告)号：US4796123A
公开(公告)日：1989-01-03
申请号：US919067
申请日：1986-10-15
申请人： Hisaharu Takeuchi , Teruo Itami
发明人： Hisaharu Takeuchi , Teruo Itami
IPC分类号： G11B15/18 , G11B15/473 , H04N5/783 , H04N5/937 , H04N5/95
CPC分类号： G11B15/4735 , G11B15/1875 , H04N5/937
摘要： In a slow reproducing apparatus, a magnetic tape is intermittently driven. In a tape stop state during the intermittent drive operation, a video signal for one field is written in a field memory, and in a tape moving state during the intermittent driving operation, the written signal is read out from the field memory. A means for correcting a read timing error of the video signal caused by a variation in tape stop position during the intermittent driving operation is used, thus obtaining a noiseless, stable, slow reproduced image.
摘要翻译：在慢速再现装置中，磁带被间歇地驱动。在间歇驱动操作期间的磁带停止状态下，将一场的视频信号写入场存储器，并且在间歇驱动操作期间，在磁带移动状态下，从场存储器读出写入的信号。使用用于校正在间歇驱动操作期间由磁带停止位置的变化引起的视频信号的读取定时误差的装置，从而获得无噪声，稳定的慢再现图像。

3. 发明授权

US5404248A Video data recording/reproducing apparatus with efficient error correction 失效
标题翻译：具有高效纠错的视频数据记录/再现装置
公开(公告)号：US5404248A
公开(公告)日：1995-04-04
申请号：US274365
申请日：1994-07-13
申请人： Kenji Shimoda , Yoshihisa Sakazaki , Hideo Tsurufusa , Minoru Yoneda , Takao Inoh , Teruo Itami
发明人： Kenji Shimoda , Yoshihisa Sakazaki , Hideo Tsurufusa , Minoru Yoneda , Takao Inoh , Teruo Itami
IPC分类号： G11B5/09 , G11B20/06 , G11B20/10 , G11B20/12 , G11B20/18 , G11B27/30 , G11B27/32 , H04N5/7826 , H04N5/92 , H04N9/804 , H04N9/806 , H04N9/82 , H04N9/83
CPC分类号： G11B20/10009 , G11B27/3063 , G11B27/324 , H04N9/8042 , H04N9/8227 , G11B2220/91 , H04N5/78263 , H04N9/8063 , H04N9/83
摘要： A video data recording/reproducing apparatus is designed to effect the high density recording for low bit rate coded data, correct the error with high reliability and reproduce only the main signal. For this purpose, an error correction circuit corrects the error in a transmission path by use of a parity code added by a parity adding circuit on the transmission side. A switch selects one of outputs of the parity adding circuit and error correction circuit according to whether the parity code is contained in the transmission data or not. A recording/reproducing circuit causes an output of the switch to be recorded. At the time of reproducing operation, the error correction circuit corrects the error in the recording/reproducing operation by use of the parity code contained in the reproduced signal.
摘要翻译：视频数据记录/再现装置被设计为实现低比特率编码数据的高密度记录，以高可靠性校正误差并仅再现主信号。为此，误差校正电路通过使用由发送侧的奇偶校验相加电路相加的奇偶校验码来校正传输路径中的误差。根据发送数据中是否包含奇偶校验码，开关选择奇偶校验相加电路和纠错电路的输出之一。记录/再现电路使得开关的输出被记录。在再现操作时，纠错电路通过使用包含在再现信号中的奇偶校验码校正记录/再现操作中的错误。

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