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1. 发明授权

US07193917B2 Semiconductor storage device, test method therefor, and test circuit therefor 失效
标题翻译：半导体存储装置及其测试方法及其测试电路
公开(公告)号：US07193917B2
公开(公告)日：2007-03-20
申请号：US10498398
申请日：2002-12-10
申请人： Hiroyuki Takahashi , Hideo Inaba , Syouzou Uchida
发明人： Hiroyuki Takahashi , Hideo Inaba , Syouzou Uchida
IPC分类号： G11C7/00
CPC分类号： G11C29/12015 , G11C8/18 , G11C11/401 , G11C11/406 , G11C29/14
摘要： A test method and a test circuit which enable operations to be checked when the time interval between a refresh operation and a read or write operation is forcibly reduced. Timings for a read or write operation in a normal operation mode and in a test mode are determined on the basis of an address transition detection circuit. A timing for a refresh operation in the normal operation mode is set on the basis of a normal refreshing pulse signal generated by a refresh pulse generating circuit in response to a timing signal generated by a timer circuit. A timing for a refresh operation in the test mode is set on the basis of a first testing refresh pulse generation signal generated by a first testing refresh pulse generating circuit in response to the address transition detection signal. By controlling a timing for generating the first testing refresh pulse generation signal, it is possible to generate a read or write operation and a refresh operation so that there is a predetermined time interval between these operations.
摘要翻译：当刷新操作和读/写操作之间的时间间隔被强制降低时，能够检查操作的测试方法和测试电路。基于地址转换检测电路来确定在正常操作模式和测试模式下进行读或写操作的时序。基于由定时器电路产生的定时信号由刷新脉冲发生电路产生的正常刷新脉冲信号来设定正常操作模式下的刷新操作的定时。基于由第一测试刷新脉冲发生电路响应于地址转换检测信号产生的第一测试刷新脉冲产生信号来设置测试模式下的刷新操作的定时。通过控制用于产生第一测试刷新脉冲产生信号的定时，可以产生读或写操作和刷新操作，使得在这些操作之间存在预定的时间间隔。

2. 发明申请

US20050207252A1 Semiconductor storage device, test method therefor, and test circuit therefor 失效
标题翻译：半导体存储装置及其测试方法及其测试电路
公开(公告)号：US20050207252A1
公开(公告)日：2005-09-22
申请号：US10498398
申请日：2002-12-10
申请人： Hiroyuki Takahashi , Hideo Inaba , Syouzou Uchida
发明人： Hiroyuki Takahashi , Hideo Inaba , Syouzou Uchida
IPC分类号： G01R31/28 , G01R31/3185 , G11C8/18 , G11C11/401 , G11C11/403 , G11C11/406 , G11C29/08 , G11C29/14 , G11C7/00
CPC分类号： G11C29/12015 , G11C8/18 , G11C11/401 , G11C11/406 , G11C29/14
摘要： A test method and a test circuit which enable operations to be checked when the time interval between a refresh operation and a read or write operation is forcibly reduced. Timings for a read or write operation in a normal operation mode and in a test mode are determined on the basis of an address transition detection circuit. A timing for a refresh operation in the normal operation mode is set on the basis of a normal refreshing pulse signal generated by a refresh pulse generating circuit in response to a timing signal generated by a timer circuit. A timing for a refresh operation in the test mode is set on the basis of a first testing refresh pulse generation signal generated by a first testing refresh pulse generating circuit in response to the address transition detection signal. By controlling a timing for generating the first testing refresh pulse generation signal, it is possible to generate a read or write operation and a refresh operation so that there is a predetermined time interval between these operations.
摘要翻译：当刷新操作和读/写操作之间的时间间隔被强制降低时，能够检查操作的测试方法和测试电路。基于地址转换检测电路来确定在正常操作模式和测试模式下进行读或写操作的时序。基于由定时器电路产生的定时信号由刷新脉冲发生电路产生的正常刷新脉冲信号来设定正常操作模式下的刷新操作的定时。基于由第一测试刷新脉冲发生电路响应于地址转换检测信号产生的第一测试刷新脉冲产生信号来设置测试模式下的刷新操作的定时。通过控制用于产生第一测试刷新脉冲产生信号的定时，可以产生读或写操作和刷新操作，使得在这些操作之间存在预定的时间间隔。

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